Volume 3B System Programming Guide_ Part 2 (794104), страница 53
Текст из файла (страница 53)
So an SMI handler that is going to trigger power down should first read theseregisters listed above directly, and save them (along with the rest of RAM) to nonvolatile storage. After the power-on reset, the continuation of the SMI handler shouldrestore these values, along with the rest of the system's state.
Anytime the SMIhandler changes these registers in the processor, it must also save and restore them.NOTESA small subset of the MSRs (such as, the time-stamp counter andperformance-monitoring counters) are not arbitrarily writable andtherefore cannot be saved and restored. SMM-based power-downand restoration should only be performed with operating systemsthat do not use or rely on the values of these registers.Operating system developers should be aware of this fact and insurethat their operating-system assisted power-down and restorationsoftware is immune to unexpected changes in these register values.24.4.1.1SMRAM State Save Map and Intel 64 ArchitectureWhen the processor initially enters SMM, it writes its state to the state save area ofthe SMRAM.
The state save area on an IA-32 processor that supports Intel 64 architecture begins at [SMBASE + 8000H + 7FFFH] and extends to [SMBASE + 8000H +7C00H].Intel 64 architecture is supported in an IA-32 processor if the processor reportsCPUID.80000001:EDX[29] = 1. The layout of the SMRAM state save map is shown inTable 24-2.24-8 Vol.
3SYSTEM MANAGEMENTTable 24-2. ISMRAM State Save Map for Intel 64 ArchitectureOffset(Added to SMBASE +8000H)RegisterWritable?7FF8HCR0No7FF0HCR3No7FE8HRFLAGSYes7FE0HIA32_EFERYes7FD8HRIPYes7FD0HDR6No7FC8HDR7No7FC4HTR SEL1No17FC0HLDTR SELNo7FBCH1GS SELNo7FB8HFS SEL1No7FB4H1No7FB0HSS SEL1No7FACHCS SEL1No7FA8HES SEL1No7FA4HIO_MISCNo7F9CHIO_MEM_ADDRNo7F94HRDIYes7F8CHRSIYes7F84HRBPYes7F7CHRSPYes7F74HRBXYes7F6CHRDXYes7F64HRCXYes7F5CHRAXYes7F54HR8Yes7F4CHR9Yes7F44HR10Yes7F3CHR11YesDS SELVol.
3 24-9SYSTEM MANAGEMENTTable 24-2. ISMRAM State Save Map for Intel 64 Architecture (Contd.)Offset(Added to SMBASE +8000H)RegisterWritable?7F34HR12Yes7F2CHR13Yes7F24HR14Yes7F1CHR15Yes7F1BH-7F04HReservedNo7F02HAuto HALT Restart Field (Word)Yes7F00HI/O Instruction Restart Field (Word)Yes7EFCHSMM Revision Identifier Field (Doubleword)No7EF8HSMBASE Field (Doubleword)Yes7EF7H - 7EA8HReservedNo7EA4HLDT InfoNo7EA0HLDT LimitNo7E9CHLDT Base (lower 32 bits)No7E98HIDT LimitNo7E94HIDT Base (lower 32 bits)No7E90HGDT LimitNo7E8CHGDT Base (lower 32 bits)No7E8BH - 7E44HReservedNo7E40HCR4No7E3FH - 7DF0HReservedNo7DE8HIO_EIPYes7DE7H - 7DDCHReservedNo7DD8HIDT Base (Upper 32 bits)No7DD4HLDT Base (Upper 32 bits)No7DD0HGDT Base (Upper 32 bits)No7DCFH - 7C00HReservedNoNOTE:1.
The two most significant bytes are reserved.24-10 Vol. 3SYSTEM MANAGEMENT24.4.2SMRAM CachingAn IA-32 processor does not automatically write back and invalidate its caches beforeentering SMM or before exiting SMM. Because of this behavior, care must be taken inthe placement of the SMRAM in system memory and in the caching of the SMRAM toprevent cache incoherence when switching back and forth between SMM andprotected mode operation. Either of the following three methods of locating theSMRAM in system memory will guarantee cache coherency:•Place the SRAM in a dedicated section of system memory that the operatingsystem and applications are prevented from accessing.
Here, the SRAM can bedesignated as cacheable (WB, WT, or WC) for optimum processor performance,without risking cache incoherence when entering or exiting SMM.•Place the SRAM in a section of memory that overlaps an area used by theoperating system (such as the video memory), but designate the SMRAM asuncacheable (UC). This method prevents cache access when in SMM to maintaincache coherency, but the use of uncacheable memory reduces the performanceof SMM code.•Place the SRAM in a section of system memory that overlaps an area used by theoperating system and/or application code, but explicitly flush (write back andinvalidate) the caches upon entering and exiting SMM mode. This methodmaintains cache coherency, but the incurs the overhead of two complete cacheflushes.For Pentium 4, Intel Xeon, and P6 family processors, a combination of the first twomethods of locating the SMRAM is recommended.
Here the SMRAM is split betweenan overlapping and a dedicated region of memory. Upon entering SMM, the SMRAMspace that is accessed overlaps video memory (typically located in low memory).This SMRAM section is designated as UC memory. The initial SMM code then jumps toa second SMRAM section that is located in a dedicated region of system memory(typically in high memory). This SMRAM section can be cached for optimumprocessor performance.For systems that explicitly flush the caches upon entering SMM (the third methoddescribed above), the cache flush can be accomplished by asserting the FLUSH# pinat the same time as the request to enter SMM (generally initiated by asserting theSMI# pin).
The priorities of the FLUSH# and SMI# pins are such that the FLUSH# isserviced first. To guarantee this behavior, the processor requires that the followingconstraints on the interaction of FLUSH# and SMI# be met. In a system where theFLUSH# and SMI# pins are synchronous and the set up and hold times are met, thenthe FLUSH# and SMI# pins may be asserted in the same clock. In asynchronoussystems, the FLUSH# pin must be asserted at least one clock before the SMI# pin toguarantee that the FLUSH# pin is serviced first.Upon leaving SMM (for systems that explicitly flush the caches), the WBINVD instruction should be executed prior to leaving SMM to flush the caches.Vol.
3 24-11SYSTEM MANAGEMENTNOTESIn systems based on the Pentium processor that use the FLUSH# pinto write back and invalidate cache contents before entering SMM, theprocessor will prefetch at least one cache line in between when theFlush Acknowledge cycle is run and the subsequent recognition ofSMI# and the assertion of SMIACT#.It is the obligation of the system to ensure that these lines are notcached by returning KEN# inactive to the Pentium processor.24.5SMI HANDLER EXECUTION ENVIRONMENTAfter saving the current context of the processor, the processor initializes its coreregisters to the values shown in Table 24-3. Upon entering SMM, the PE and PG flagsin control register CR0 are cleared, which places the processor is in an environmentsimilar to real-address mode.
The differences between the SMM execution environment and the real-address mode execution environment are as follows:•The addressable SMRAM address space ranges from 0 to FFFFFFFFH (4 GBytes).(The physical address extension (enabled with the PAE flag in control registerCR4) is not supported in SMM.)•The normal 64-KByte segment limit for real-address mode is increased to4 GBytes.•The default operand and address sizes are set to 16 bits, which restricts theaddressable SMRAM address space to the 1-MByte real-address mode limit fornative real-address-mode code.
However, operand-size and address-sizeoverride prefixes can be used to access the address space beyond the 1-MByte.Table 24-3. Processor Register Initialization in SMMRegisterContentsGeneral-purpose registersUndefinedEFLAGS00000002HEIP00008000HCS selectorSMM Base shifted right 4 bits (default 3000H)CS baseSMM Base (default 30000H)DS, ES, FS, GS, SS Selectors0000HDS, ES, FS, GS, SS Bases000000000HDS, ES, FS, GS, SS Limits0FFFFFFFFHCR0PE, EM, TS, and PG flags set to 0; others unmodifiedCR4Cleared to zeroDR6UndefinedDR700000400H24-12 Vol. 3SYSTEM MANAGEMENT•Near jumps and calls can be made to anywhere in the 4-GByte address space if a32-bit operand-size override prefix is used. Due to the real-address-mode styleof base-address formation, a far call or jump cannot transfer control to asegment with a base address of more than 20 bits (1 MByte).
However, since thesegment limit in SMM is 4 GBytes, offsets into a segment that go beyond the1-MByte limit are allowed when using 32-bit operand-size override prefixes. Anyprogram control transfer that does not have a 32-bit operand-size override prefixtruncates the EIP value to the 16 low-order bits.•Data and the stack can be located anywhere in the 4-GByte address space, butcan be accessed only with a 32-bit address-size override if they are located above1 MByte. As with the code segment, the base address for a data or stack segmentcannot be more than 20 bits.The value in segment register CS is automatically set to the default of 30000H for theSMBASE shifted 4 bits to the right; that is, 3000H.
The EIP register is set to 8000H.When the EIP value is added to shifted CS value (the SMBASE), the resulting linearaddress points to the first instruction of the SMI handler.The other segment registers (DS, SS, ES, FS, and GS) are cleared to 0 and theirsegment limits are set to 4 GBytes. In this state, the SMRAM address space may betreated as a single flat 4-GByte linear address space. If a segment register is loadedwith a 16-bit value, that value is then shifted left by 4 bits and loaded into thesegment base (hidden part of the segment register). The limits and attributes are notmodified.Maskable hardware interrupts, exceptions, NMI interrupts, SMI interrupts, A20Minterrupts, single-step traps, breakpoint traps, and INIT operations are inhibitedwhen the processor enters SMM.
Maskable hardware interrupts, exceptions, singlestep traps, and breakpoint traps can be enabled in SMM if the SMM execution environment provides and initializes an interrupt table and the necessary interrupt andexception handlers (see Section 24.6).24.6EXCEPTIONS AND INTERRUPTS WITHIN SMMWhen the processor enters SMM, all hardware interrupts are disabled in the followingmanner:•The IF flag in the EFLAGS register is cleared, which inhibits maskable hardwareinterrupts from being generated.••The TF flag in the EFLAGS register is cleared, which disables single-step traps.•NMI, SMI, and A20M interrupts are blocked by internal SMM logic.
![](https://s.studizba.com/z.php?f=/templates/si/i/noavatar.png&w=100&h=100&t=1"){kind=avatar}
