Volume 3B System Programming Guide_ Part 2 (794104), страница 55
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3 24-17SYSTEM MANAGEMENTThe SMI handler may continue to execute in protected mode after the x87 FPU statehas been saved and return safely to the interrupted program from protected mode.However, it is recommended that the handler execute primarily in 16- or 32-bit realaddress mode.24.10SMM REVISION IDENTIFIERThe SMM revision identifier field is used to indicate the version of SMM and the SMMextensions that are supported by the processor (see Figure 24-2). The SMM revisionidentifier is written during SMM entry and can be examined in SMRAM space at offset7EFCH. The lower word of the SMM revision identifier refers to the version of the baseSMM architecture.Register Offset7EFCH31018 17 16 15ReservedSMM Revision IdentifierSMBASE RelocationI/O Instruction RestartFigure 24-2.
SMM Revision IdentifierThe upper word of the SMM revision identifier refers to the extensions available. Ifthe I/O instruction restart flag (bit 16) is set, the processor supports the I/O instruction restart (see Section 24.13); if the SMBASE relocation flag (bit 17) is set, SMRAMbase address relocation is supported (see Section 24.12).24.11AUTO HALT RESTARTIf the processor is in a HALT state (due to the prior execution of a HLT instruction)when it receives an SMI, the processor records the fact in the auto HALT restart flagin the saved processor state (see Figure 24-3).
(This flag is located at offset 7F02Hand bit 0 in the state save area of the SMRAM.)If the processor sets the auto HALT restart flag upon entering SMM (indicating thatthe SMI occurred when the processor was in the HALT state), the SMI handler hastwo options:•It can leave the auto HALT restart flag set, which instructs the RSM instruction toreturn program control to the HLT instruction. This option in effect causes the24-18 Vol. 3SYSTEM MANAGEMENTprocessor to re-enter the HALT state after handling the SMI. (This is the defaultoperation.)•It can clear the auto HALT restart flag, with instructs the RSM instruction toreturn program control to the instruction following the HLT instruction.151 0ReservedRegister Offset7F02HAuto HALT RestartFigure 24-3.
Auto HALT Restart FieldThese options are summarized in Table 24-6. Note that if the processor was not in aHALT state when the SMI was received (the auto HALT restart flag is cleared), settingthe flag to 1 will cause unpredictable behavior when the RSM instruction is executed.Table 24-6. Auto HALT Restart Flag ValuesValue of FlagAfter Entry toSMMValue of FlagAction of Processor When Exiting SMMWhen Exiting SMM00Returns to next instruction in interrupted program or task.01Unpredictable.10Returns to next instruction after HLT instruction.11Returns to HALT state.If the HLT instruction is restarted, the processor will generate a memory access tofetch the HLT instruction (if it is not in the internal cache), and execute a HLT bustransaction.
This behavior results in multiple HLT bus transactions for the same HLTinstruction.24.11.1 Executing the HLT Instruction in SMMThe HLT instruction should not be executed during SMM, unless interrupts have beenenabled by setting the IF flag in the EFLAGS register. If the processor is halted inSMM, the only event that can remove the processor from this state is a maskablehardware interrupt or a hardware reset.Vol. 3 24-19SYSTEM MANAGEMENT24.12SMBASE RELOCATIONThe default base address for the SMRAM is 30000H. This value is contained in aninternal processor register called the SMBASE register.
The operating system orexecutive can relocate the SMRAM by setting the SMBASE field in the saved statemap (at offset 7EF8H) to a new value (see Figure 24-4). The RSM instruction reloadsthe internal SMBASE register with the value in the SMBASE field each time it exitsSMM. All subsequent SMI requests will use the new SMBASE value to find the startingaddress for the SMI handler (at SMBASE + 8000H) and the SMRAM state save area(from SMBASE + FE00H to SMBASE + FFFFH). (The processor resets the value in itsinternal SMBASE register to 30000H on a RESET, but does not change it on an INIT.)310SMM BaseRegister Offset7EF8HFigure 24-4. SMBASE Relocation FieldIn multiple-processor systems, initialization software must adjust the SMBASE valuefor each processor so that the SMRAM state save areas for each processor do notoverlap.
(For Pentium and Intel486 processors, the SMBASE values must be alignedon a 32-KByte boundary or the processor will enter shutdown state during the execution of a RSM instruction.)If the SMBASE relocation flag in the SMM revision identifier field is set, it indicates theability to relocate the SMBASE (see Section 24.10).24.12.1 Relocating SMRAM to an Address Above 1 MByteIn SMM, the segment base registers can only be updated by changing the value in thesegment registers. The segment registers contain only 16 bits, which allows only 20bits to be used for a segment base address (the segment register is shifted left 4 bitsto determine the segment base address). If SMRAM is relocated to an address above1 MByte, software operating in real-address mode can no longer initialize thesegment registers to point to the SMRAM base address (SMBASE).The SMRAM can still be accessed by using 32-bit address-size override prefixes togenerate an offset to the correct address.
For example, if the SMBASE has been relocated to FFFFFFH (immediately below the 16-MByte boundary) and the DS, ES, FS,and GS registers are still initialized to 0H, data in SMRAM can be accessed by using32-bit displacement registers, as in the following example:movmov24-20 Vol. 3esi,00FFxxxxH; 64K segment immediately below 16Max,ds:[esi]SYSTEM MANAGEMENTA stack located above the 1-MByte boundary can be accessed in the same manner.24.13I/O INSTRUCTION RESTARTIf the I/O instruction restart flag in the SMM revision identifier field is set (see Section24.10), the I/O instruction restart mechanism is present on the processor.
Thismechanism allows an interrupted I/O instruction to be re-executed upon returningfrom SMM mode. For example, if an I/O instruction is used to access a powered-downI/O device, a chip set supporting this device can intercept the access and respond byasserting SMI#. This action invokes the SMI handler to power-up the device. Uponreturning from the SMI handler, the I/O instruction restart mechanism can be used tore-execute the I/O instruction that caused the SMI.The I/O instruction restart field (at offset 7F00H in the SMM state-save area, seeFigure 24-5) controls I/O instruction restart.
When an RSM instruction is executed, ifthis field contains the value FFH, then the EIP register is modified to point to the I/Oinstruction that received the SMI request. The processor will then automatically reexecute the I/O instruction that the SMI trapped. (The processor saves the necessarymachine state to insure that re-execution of the instruction is handled coherently.)150I/O Instruction Restart FieldRegister Offset7F00HFigure 24-5. I/O Instruction Restart FieldIf the I/O instruction restart field contains the value 00H when the RSM instruction isexecuted, then the processor begins program execution with the instruction followingthe I/O instruction.
(When a repeat prefix is being used, the next instruction may bethe next I/O instruction in the repeat loop.) Not re-executing the interrupted I/Oinstruction is the default behavior; the processor automatically initializes the I/Oinstruction restart field to 00H upon entering SMM. Table 24-7 summarizes the statesof the I/O instruction restart field.Table 24-7. I/O Instruction Restart Field ValuesValue of Flag AfterEntry to SMMValue of Flag WhenExiting SMMAction of Processor When Exiting SMM00H00HDoes not re-execute trapped I/O instruction.00HFFHRe-executes trapped I/O instruction.Note that the I/O instruction restart mechanism does not indicate the cause of theSMI. It is the responsibility of the SMI handler to examine the state of the processorto determine the cause of the SMI and to determine if an I/O instruction was inter-Vol.
3 24-21SYSTEM MANAGEMENTrupted and should be restarted upon exiting SMM. If an SMI interrupt is signaled ona non-I/O instruction boundary, setting the I/O instruction restart field to FFH prior toexecuting the RSM instruction will likely result in a program error.24.13.1 Back-to-Back SMI Interrupts When I/O Instruction Restart IsBeing UsedIf an SMI interrupt is signaled while the processor is servicing an SMI interrupt thatoccurred on an I/O instruction boundary, the processor will service the new SMIrequest before restarting the originally interrupted I/O instruction. If the I/O instruction restart field is set to FFH prior to returning from the second SMI handler, the EIPwill point to an address different from the originally interrupted I/O instruction, whichwill likely lead to a program error.
To avoid this situation, the SMI handler must beable to recognize the occurrence of back-to-back SMI interrupts when I/O instructionrestart is being used and insure that the handler sets the I/O instruction restart fieldto 00H prior to returning from the second invocation of the SMI handler.24.14SMM MULTIPLE-PROCESSOR CONSIDERATIONSThe following should be noted when designing multiple-processor systems:••Any processor in a multiprocessor system can respond to an SMM.•The SMRAMs for different processors can be overlapped in the same memoryspace. The only stipulation is that each processor needs its own state save areaand its own dynamic data storage area.
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