Volume 3B System Programming Guide_ Part 2 (794104), страница 52
Текст из файла (страница 52)
For the Pentium and Intel486 processors,the SMIACT# pin is asserted.Vol. 3 24-3SYSTEM MANAGEMENTAn SMI has a greater priority than debug exceptions and external interrupts. Thus, ifan NMI, maskable hardware interrupt, or a debug exception occurs at an instructionboundary along with an SMI, only the SMI is handled. Subsequent SMI requests arenot acknowledged while the processor is in SMM. The first SMI interrupt request thatoccurs while the processor is in SMM (that is, after SMM has been acknowledged toexternal hardware) is latched and serviced when the processor exits SMM with theRSM instruction.
The processor will latch only one SMI while in SMM.See Section 24.5 for a detailed description of the execution environment when inSMM.24.3.2Exiting From SMMThe only way to exit SMM is to execute the RSM instruction. The RSM instruction isonly available to the SMI handler; if the processor is not in SMM, attempts to executethe RSM instruction result in an invalid-opcode exception (#UD) being generated.The RSM instruction restores the processor’s context by loading the state save imagefrom SMRAM back into the processor’s registers. The processor then returns anSMIACK transaction on the system bus and returns program control back to theinterrupted program.Upon successful completion of the RSM instruction, the processor signals externalhardware that SMM has been exited.
For the P6 family processors, an SMI acknowledge transaction is generated on the system bus and the multiplexed status signalEXF4 is no longer generated on bus cycles. For the Pentium and Intel486 processors,the SMIACT# pin is deserted.If the processor detects invalid state information saved in the SMRAM, it enters theshutdown state and generates a special bus cycle to indicate it has entered shutdownstate. Shutdown happens only in the following situations:•A reserved bit in control register CR4 is set to 1 on a write to CR4.
This errorshould not happen unless SMI handler code modifies reserved areas of theSMRAM saved state map (see Section 24.4.1). Note that CR4 is saved in the statemap in a reserved location and cannot be read or modified in its saved state.•An illegal combination of bits is written to control register CR0, in particular PGset to 1 and PE set to 0, or NW set to 1 and CD set to 0.•(For the Pentium and Intel486 processors only.) If the address stored in theSMBASE register when an RSM instruction is executed is not aligned on a32-KByte boundary.
This restriction does not apply to the P6 family processors.In the shutdown state, Intel processors stop executing instructions until a RESET#,INIT# or NMI# is asserted. While Pentium family processors recognize the SMI#signal in shutdown state, P6 family and Intel486 processors do not. Intel does notsupport using SMI# to recover from shutdown states for any processor family; theresponse of processors in this circumstance is not well defined. On Pentium 4 andlater processors, shutdown will inhibit INTR and A20M but will not change any of the24-4 Vol. 3SYSTEM MANAGEMENTother inhibits.
On these processors, NMIs will be inhibited if no action is taken in theSMM handler to uninhibit them (see Section 24.8).If the processor is in the HALT state when the SMI is received, the processor handlesthe return from SMM slightly differently (see Section 24.11). Also, the SMBASEaddress can be changed on a return from SMM (see Section 24.12).24.4SMRAMWhile in SMM, the processor executes code and stores data in the SMRAM space. TheSMRAM space is mapped to the physical address space of the processor and can beup to 4 GBytes in size.
The processor uses this space to save the context of theprocessor and to store the SMI handler code, data and stack. It can also be used tostore system management information (such as the system configuration andspecific information about powered-down devices) and OEM-specific information.The default SMRAM size is 64 KBytes beginning at a base physical address in physicalmemory called the SMBASE (see Figure 24-1). The SMBASE default value following ahardware reset is 30000H. The processor looks for the first instruction of the SMIhandler at the address [SMBASE + 8000H].
It stores the processor’s state in the areafrom [SMBASE + FE00H] to [SMBASE + FFFFH]. See Section 24.4.1 for a descriptionof the mapping of the state save area.The system logic is minimally required to decode the physical address range for theSMRAM from [SMBASE + 8000H] to [SMBASE + FFFFH]. A larger area can bedecoded if needed. The size of this SMRAM can be between 32 KBytes and 4 GBytes.The location of the SMRAM can be changed by changing the SMBASE value (seeSection 24.12). It should be noted that all processors in a multiple-processor systemare initialized with the same SMBASE value (30000H).
Initialization software mustsequentially place each processor in SMM and change its SMBASE so that it does notoverlap those of other processors.The actual physical location of the SMRAM can be in system memory or in a separateRAM memory. The processor generates an SMI acknowledge transaction (P6 familyprocessors) or asserts the SMIACT# pin (Pentium and Intel486 processors) when theprocessor receives an SMI (see Section 24.3.1).System logic can use the SMI acknowledge transaction or the assertion of theSMIACT# pin to decode accesses to the SMRAM and redirect them (if desired) tospecific SMRAM memory. If a separate RAM memory is used for SMRAM, system logicshould provide a programmable method of mapping the SMRAM into system memoryspace when the processor is not in SMM.
This mechanism will enable start-up procedures to initialize the SMRAM space (that is, load the SMI handler) before executingthe SMI handler during SMM.Vol. 3 24-5SYSTEM MANAGEMENT24.4.1SMRAM State Save MapWhen an IA-32 processor that does not support Intel 64 architecture initially entersSMM, it writes its state to the state save area of the SMRAM. The state save areabegins at [SMBASE + 8000H + 7FFFH] and extends down to [SMBASE + 8000H +7E00H]. Table 24-1 shows the state save map. The offset in column 1 is relative tothe SMBASE value plus 8000H. Reserved spaces should not be used by software.Some of the registers in the SMRAM state save area (marked YES in column 3) maybe read and changed by the SMI handler, with the changed values restored to theprocessor registers by the RSM instruction.
Some register images are read-only, andmust not be modified (modifying these registers will result in unpredictablebehavior). An SMI handler should not rely on any values stored in an area that ismarked as reserved.SMRAMSMBASE + FFFFHSMBASE + 8000HStart of State Save AreaSMI Handler Entry PointSMBASEFigure 24-1. SMRAM UsageTable 24-1. SMRAM State Save MapOffset(Added to SMBASE +8000H)RegisterWritable?7FFCHCR0No7FF8HCR3No7FF4HEFLAGSYes7FF0HEIPYes7FECHEDIYes7FE8HESIYes7FE4HEBPYes7FE0HESPYes24-6 Vol.
3SYSTEM MANAGEMENTTable 24-1. SMRAM State Save Map (Contd.)Offset(Added to SMBASE +8000H)RegisterWritable?7FDCHEBXYes7FD8HEDXYes7FD4HECXYes7FD0HEAXYes7FCCHDR6No7FC8HDR7No7FC4H1TRNo7FC0HReservedNo7FBCHGS1No7FB8H1No7FB4HDS1No7FB0HSS1No7FACH1No1FSCS7FA8HESNo7FA4HI/O State Field, see Section 24.7No7FA0HI/O Memory Address Field, see Section 24.7No7F9FH-7F03HReservedNo7F02HAuto HALT Restart Field (Word)Yes7F00HI/O Instruction Restart Field (Word)Yes7EFCHSMM Revision Identifier Field (Doubleword)No7EF8HSMBASE Field (Doubleword)Yes7EF7H - 7E00HReservedNoNOTE:1.
The two most significant bytes are reserved.The following registers are saved (but not readable) and restored upon exiting SMM:••Control register CR4. (This register is cleared to all 0s while in SMM).The hidden segment descriptor information stored in segment registers CS, DS,ES, FS, GS, and SS.Vol. 3 24-7SYSTEM MANAGEMENTIf an SMI request is issued for the purpose of powering down the processor, thevalues of all reserved locations in the SMM state save must be saved to nonvolatilememory.The following state is not automatically saved and restored following an SMI and theRSM instruction, respectively:•••••Debug registers DR0 through DR3.••••The state of the trap controller.The x87 FPU registers.The MTRRs.Control register CR2.The model-specific registers (for the P6 family and Pentium processors) or testregisters TR3 through TR7 (for the Pentium and Intel486 processors).The machine-check architecture registers.The APIC internal interrupt state (ISR, IRR, etc.).The microcode update state.If an SMI is used to power down the processor, a power-on reset will be requiredbefore returning to SMM, which will reset much of this state back to its defaultvalues.
![](https://s.studizba.com/z.php?f=/templates/si/i/noavatar.png&w=100&h=100&t=1"){kind=avatar}
