Volume 3B System Programming Guide_ Part 2 (794104), страница 58
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3 24-31SYSTEM MANAGEMENTVM entries that return from SMM and that do not deactivate the dual-monitor treatment may leave SMIs blocked. This feature exists to allow an SMM monitor to invokefunctionality outside of SMM without unblocking SMIs.24.16.4.8 Failures of VM Entries That Return from SMMSection 22.7 describes the treatment of VM entries that fail during or after loadingguest state. Such failures record information in the VM-exit information fields andload processor state as would be done on a VM exit.
The VMCS used is the one thatwas current before the VM entry commenced. Control is thus transferred to the SMMmonitor and the logical processor remains in SMM.24.16.5 Enabling the Dual-Monitor TreatmentCode and data for the SMM monitor reside in a region of SMRAM called the monitorsegment (MSEG). Code running in SMM determines the location of MSEG and establishes its content. This code is also responsible for enabling the dual-monitor treatment.SMM code enables the dual-monitor treatment and determines the location of MSEGby writing to IA32_SMM_MONITOR_CTL MSR (index 9BH).
The MSR has the followingformat:•Bit 0 is the register’s valid bit. The SMM monitor may be invoked using VMCALLonly if this bit is 1. Because VMCALL is used to activate the dual-monitortreatment (see Section 24.16.6), the dual-monitor treatment cannot beactivated if the bit is 0. This bit is cleared when the logical processor is reset.••Bits 11:1 are reserved.•Bits 63:32 are reserved.Bits 31:12 contain a value that, when shifted right 12 bits, is the physical addressof MSEG (the MSEG base address).The following items detail use of this MSR:•The IA32_SMM_MONITOR_CTL MSR is supported only on processors that supportthe dual-monitor treatment.1 On other processors, accesses to the MSR usingRDMSR or WRMSR generate a general-protection fault (#GP(0)).•A write to the IA32_SMM_MONITOR_CTL MSR using WRMSR generates ageneral-protection fault (#GP(0)) if executed outside of SMM or if an attempt ismade to set any reserved bit.
An attempt to write to IA32_SMM_MONITOR_CTLMSR fails if made as part of a VM exit that does not end in SMM or part of aVM entry that does not begin in SMM.1. Software should consult the VMX capability MSR IA32_VMX_BASIC (see Appendix G.1) to determine whether the dual-monitor treatment is supported.24-32 Vol.
3SYSTEM MANAGEMENT•Reads from IA32_SMM_MONITOR_CTL MSR using RDMSR are allowed any timeRDMSR is allowed. The MSR may be read as part of any VM exit.•The dual-monitor treatment can be activated only if the valid bit in the MSR is setto 1.The 32 bytes located at the MSEG base address are called the MSEG header. Theformat of the MSEG header is given in Table 24-9 (each field is 32 bits).Table 24-9. Format of MSEG HeaderByte OffsetField0MSEG-header revision identifier4SMM-monitor features8GDTR limit12GDTR base offset16CS selector20EIP offset24ESP offset28CR3 offsetTo ensure proper behavior in VMX operation, software should maintain the MSEGheader in writeback cacheable memory. Future implementations may allow orrequire a different memory type.1 Software should consult the VMX capability MSRIA32_VMX_BASIC (see Appendix G.1).SMM code should enable the dual-monitor treatment (by setting the valid bit inIA32_SMM_MONITOR_CTL MSR) only after establishing the content of the MSEGheader as follows:•Bytes 3:0 contain the MSEG revision identifier.
Different processors may usedifferent MSEG revision identifiers. These identifiers enable software to avoidusing an MSEG header formatted for one processor on a processor that uses adifferent format. Software can discover the MSEG revision identifier that aprocessor uses by reading the VMX capability MSR IA32_VMX_MISC (seeAppendix G.5).1. Alternatively, software may map the MSEG header with the UC memory type; this may be necessary, depending on how memory is organized. Doing so is strongly discouraged unless necessaryas it will cause the performance of transitions using those structures to suffer significantly.
Inaddition, the processor will continue to use the memory type reported in the VMX capability MSRIA32_VMX_BASIC with exceptions noted in Appendix G.1.Vol. 3 24-33SYSTEM MANAGEMENT•Bytes 7:4 contain the SMM-monitor features field. Bits 31:1 of this field arereserved and must be zero. Bit 0 of the field is the IA-32e mode SMM featurebit.1 It indicates whether the logical processor will be in IA-32e mode after theSMM monitor is activated (see Section 24.16.6).•Bytes 31:8 contain fields that determine how processor state is loaded when theSMM monitor is activated (see Section 24.16.6.4). SMM code should establishthese fields so that activating of the SMM monitor invokes the SMM monitor’sinitialization code.24.16.6 Activating the Dual-Monitor TreatmentThe dual-monitor treatment may be enabled by SMM code as described in Section24.16.5.
The dual-monitor treatment is activated only if it is enabled and only by theexecutive monitor. The executive monitor activates the dual-monitor treatment byexecuting VMCALL in VMX root operation.When VMCALL activates the dual-monitor treatment, it causes an SMM VM exit.Differences between this SMM VM exit and other SMM VM exits are discussed inSections 24.16.6.1 through 24.16.6.5.
See also “VMCALL—Call to VM Monitor” inChapter 5 of Intel® 64 and IA-32 Architectures Software Developer’s Manual,Volume 2B.24.16.6.1 Initial ChecksAn execution of VMCALL attempts to activate the dual-monitor treatment if (1) theprocessor supports the dual-monitor treatment;2 (2) the logical processor is in VMXroot operation; (3) the logical processor is outside SMM and the valid bit is set in theIA32_SMM_MONITOR_CTL MSR; (4) the logical processor is not in virtual-8086mode and not in compatibility mode; (5) CPL = 0; and (6) the dual-monitor treatment is not active.The VMCS that manages SMM VM exit caused by this VMCALL is the current VMCSestablished by the executive monitor. The VMCALL performs the following checks onthe current VMCS in the order indicated:1.
There must be a current VMCS pointer.2. The launch state of the current VMCS must be clear.1. Note that use of IA-32e mode address-translation mechanism is not currently supported in SMM.Thus, setting the IA-32e mode SMM feature bit to 1 is not currently supported. See note inSection 24.1.2.
Software should consult the VMX capability MSR IA32_VMX_BASIC (see Appendix G.1) to determine whether the dual-monitor treatment is supported.24-34 Vol. 3SYSTEM MANAGEMENT3. The VM-exit control fields must be valid:— Reserved bits in the VM-exit controls must be set properly. Software mayconsult the VMX capability MSR IA32_VMX_EXIT_CTLS to determine theproper settings (see Appendix G.3).— The following checks are performed for the VM-exit MSR-store address if theVM-exit MSR-store count field is non-zero:•The lower 4 bits of the VM-exit MSR-store address must be 0.
Onprocessors that support Intel 64 architecture, the address should not setany bits beyond the processor’s physical-address width.1 On processorsthat do not support Intel 64 architecture, the address should not set anybits in the range 63:32.•On processors that support Intel 64 architecture, the address of the lastbyte in the VM-exit MSR-store area should not set any bits beyond theprocessor’s physical-address width.
On processors that do not supportIntel 64 architecture, the address of the last byte in the VM-exit MSRstore area should not set any bits in the range 63:32. The address of thislast byte is VM-exit MSR-store address + (MSR count * 16) – 1. (Thearithmetic used for the computation uses more bits than the processor’sphysical-address width.)If any of these checks fail, subsequent checks are skipped and VMCALL fails. If allthese checks succeed, the logical processor uses the IA32_SMM_MONITOR_CTL MSRto determine the base address of MSEG. The following checks are performed in theorder indicated:1.
The logical processor reads the 32 bits at the base of MSEG and compares themto the processor’s MSEG revision identifier.2. The logical processor reads the SMM-monitor features field:— Bit 0 of the field is the IA-32e mode SMM feature bit, and it indicates whetherthe logical processor will be in IA-32e mode after the SMM monitor isactivated.•If the VMCALL is executed on a processor that does not support Intel 64architecture, the IA-32e mode SMM feature bit must be 0.•If the VMCALL is executed in 64-bit mode, the IA-32e mode SMM featurebit must be 1.— Bits 31:1 of this field are currently reserved and must be zero.If any of these checks fail, subsequent checks are skipped and the VMCALL fails.1. Software can determine a processor’s physical-address width by executing CPUID with80000008H in EAX.
The physical-address width is returned in bits 7:0 of EAX.Vol. 3 24-35SYSTEM MANAGEMENT24.16.6.2 MSEG CheckingSMM VM exits that activate the dual-monitor treatment check the following beforeupdating the current-VMCS pointer and the executive-VMCS pointer field (seeSection 24.16.2.2):•The 32 bits at the MSEG base address (used as a physical address) must containthe processor’s MSEG revision identifier.•Bits 31:1 of the SMM-monitor features field in the MSEG header (see Table 24-9)must be 0.
Bit 0 of the field (the IA-32e mode SMM feature bit) must be 0 if theprocessor does not support Intel 64 architecture.If either of these checks fail, execution of VMCALL fails.24.16.6.3 Updating the Current-VMCS and Executive-VMCS PointersBefore performing the steps in Section 24.16.2.2, SMM VM exits that activate thedual-monitor treatment begin by loading the SMM-transfer VMCS pointer with thevalue of the current-VMCS pointer.24.16.6.4 Loading Host StateThe VMCS that is current during an SMM VM exit that activates the dual-monitortreatment was established by the executive monitor. It does not contain the VM-exitcontrols and host state required to initialize the SMM monitor.
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