Volume 3B System Programming Guide_ Part 2 (794104), страница 60
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Consequently, werecommend that the VMM remove any linear-address mappings toVMCS regions before loading.System software does not need to do special preparation to the VMXON region beforeentering into VMX operation. The address of the VMXON region for the VMM isprovided as an operand to VMXON instruction. Once in VMX root operation, the VMMneeds to prepare data fields in the VMCS that control the execution of a VM upon aVM entry. The VMM can make a VMCS the current VMCS by using the VMPTRLDinstruction. VMCS data fields must be read or written only through VMREAD andVMWRITE commands respectively.Every component of the VMCS is identified by a 32-bit encoding that is provided asan operand to VMREAD and VMWRITE.
Appendix H provides the encodings. A VMMmust properly initialize all fields in a VMCS before using the current VMCS for VMentry.A VMCS is referred to as a controlling VMCS if it is the current VMCS on a logicalprocessor in VMX non-root operation. A current VMCS for controlling a logicalprocessor in VMX non-root operation may be referred to as a working VMCS if thelogical processor is not in VMX non-root operation. The relationship of active, current(i.e. working) and controlling VMCS during VMX operation is shown in Figure 25-1.The VMX capability MSR IA32_VMX_BASIC reports the memory type used by theprocessor for accessing a VMCS or any data structures referenced through pointers inthe VMCS.
Software must maintain the VMCS structures in cache-coherent memory.Software must always map the regions hosting the I/O bitmaps, MSR bitmaps, VMexit MSR-store area, VM-exit MSR-load area, and VM-entry MSR-load area to thewrite-back (WB) memory type. Mapping these regions to uncacheable (UC) memorytype is supported, but strongly discouraged due to negative impact on performance.Vol. 3 25-3VIRTUAL-MACHINE MONITOR PROGRAMMING CONSIDERATIONS(a) VMX Operation and VMX TransitionsVM EntryVM EntryVM EntryVM EntryVMXOFFProcessorOperationVM ExitVM ExitVM ExitVMXONVM ExitLegend:OutsideVMXOperationVMX RootOperationVMXNon-RootOperation(b) State of VMCS and VMX OperationVMResume BVMLaunch AVMLaunch BVMPtrLd BVMResume AVMClear BVMXOFFVMCS BVMCS AVMClear AVMPtrld ALegend:InvalidVMCSVM ExitVM ExitVM ExitVMPtrLd AVM ExitVMClear ACurrentVMCSActive VMCSControllingVMCSOM19042Figure 25-1.
VMX Transitions and States of VMCS in a Logical Processor25-4 Vol. 3VIRTUAL-MACHINE MONITOR PROGRAMMING CONSIDERATIONS25.4USING VMX INSTRUCTIONSVMX instructions are allowed only in VMX root operation. An attempt to execute aVMX instruction in VMX non-root operation causes a VM exit.Processors perform various checks while executing any VMX instruction. They followwell-defined error handling on failures. VMX instruction execution failures detectedbefore loading of a guest state are handled by the processor as follows:••If the working-VMCS is not valid, the instruction fails by setting RFLAGS.CF = 1.If the working-VMCS pointer is valid, RFLAGS.ZF is set to value 1 and the propererror-code is saved in the VM-instruction error field of the working-VMCS.Software is required to check RFLAGS.CF and RFLAGS.ZF to determine the success orfailure of VMX instruction executions.After a VM-entry instruction (VMRESUME or VMLAUNCH) successfully completes thegeneral checks and checks on VMX controls and the host-state area (see Section22.2), any errors encountered while loading of guest-state (due to bad guest-state orbad MSR loading) causes the processor to load state from the host-state area of theworking VMCS as if a VM exit had occurred (see Section 25.7).This failure behavior differs from that of VM exits in that no guest-state is saved tothe guest-state area.
A VMM can detect its VM-exit handler was invoked by such afailure by checking bit 31 (for 1) in the exit reason field of the working VMCS andfurther identify the failure by using the exit qualification field.25.5VMM SETUP & TEAR DOWNVMMs need to ensure that the processor is running in protected mode with pagingbefore entering VMX operation. The following list describes the minimal stepsrequired to enter VMX root operation with a VMM running at CPL = 0.••Check VMX support in processor using CPUID.•Create a VMXON region in non-pageable memory of a size specified byIA32_VMX_BASIC MSR and aligned to a 4-KByte boundary. Software should readthe capability MSRs to determine width of the physical addresses that may beused for the VMXON region and ensure the entire VMXON region can beaddressed by addresses with that width.
Also, software must ensure that theVMXON region is hosted in cache-coherent memory.•Initialize the version identifier in the VMXON region (the first 32 bits) with theVMCS revision identifier reported by capability MSRs.•Ensure the current processor operating mode meets the required CR0 fixed bits(CR0.PE = 1, CR0.PG = 1). Other required CR0 fixed bits can be detectedthrough the IA32_VMX_CR0_FIXED0 and IA32_VMX_CR0_FIXED1 MSRs.Determine the VMX capabilities supported by the processor through the VMXcapability MSRs.
See Appendix G.Vol. 3 25-5VIRTUAL-MACHINE MONITOR PROGRAMMING CONSIDERATIONS•Enable VMX operation by setting CR4.VMXE = 1. Ensure the resultant CR4 valuesupports all the CR4 fixed bits reported in the IA32_VMX_CR4_FIXED0 andIA32_VMX_CR4_FIXED1 MSRs.•Ensure that the IA32_FEATURE_CONTROL MSR (MSR index 3AH) has beenproperly programmed and that its lock bit is set (Bit 0 = 1). This MSR is generallyconfigured by the BIOS using WRMSR.•Execute VMXON with the physical address of the VMXON region as the operand.Check successful execution of VMXON by checking if RFLAGS.CF = 0.Upon successful execution of the steps above, the processor is in VMX root operation.A VMM executing in VMX root operation and CPL = 0 leaves VMX operation byexecuting VMXOFF and verifies successful execution by checking if RFLAGS.CF = 0and RFLAGS.ZF = 0.If an SMM monitor (see Section 24.16) has been configured to service SMIs while inVMX operation, the SMM monitor needs to be torn down before the executive monitor(see Section 24.16.7) can leave VMX operation.
VMXOFF fails for the executivemonitor (a VMM that entered VMX operation by way of issuing VMXON) if SMMmonitor is configured.25.6PREPARATION AND LAUNCHING A VIRTUALMACHINEThe following list describes the minimal steps required by the VMM to set up andlaunch a guest VM.•Create a VMCS region in non-pageable memory of size specified by the VMXcapability MSR IA32_VMX_BASIC and aligned to 4-KBytes.
Software should readthe capability MSRs to determine width of the physical addresses that may beused for a VMCS region and ensure the entire VMCS region can be addressed byaddresses with that width. The term “guest-VMCS address” refers to the physicaladdress of the new VMCS region for the following steps.•Initialize the version identifier in the VMCS (first 32 bits) with the VMCS revisionidentifier reported by the VMX capability MSR IA32_VMX_BASIC.•Execute the VMCLEAR instruction by supplying the guest-VMCS address. This willinitialize the new VMCS region in memory and set the launch state of the VMCSto “clear”.
This action also invalidates the working-VMCS pointer register toFFFFFFFF_FFFFFFFFH. Software should verify successful execution of VMCLEARby checking if RFLAGS.CF = 0 and RFLAGS.ZF = 0.•Execute the VMPTRLD instruction by supplying the guest-VMCS address. Thisinitializes the working-VMCS pointer with the new VMCS region’s physicaladdress.•Issue a sequence of VMWRITEs to initialize various host-state area fields in theworking VMCS.
The initialization sets up the context and entry-points to the VMM25-6 Vol. 3VIRTUAL-MACHINE MONITOR PROGRAMMING CONSIDERATIONSupon subsequent VM exits from the guest. Host-state fields include controlregisters (CR0, CR3 and CR4), selector fields for the segment registers (CS, SS,DS, ES, FS, GS and TR), and base-address fields (for FS, GS, TR, GDTR and IDTR;RSP, RIP and the MSRs that control fast system calls).Chapter 22 describes the host-state consistency checking done by the processorfor VM entries.
The VMM is required to set up host-state that comply with theseconsistency checks. For example, VMX requires the host-area to have a taskregister (TR) selector with TI and RPL fields set to 0 and pointing to a valid TSS.•Use VMWRITEs to set up the various VM-exit control fields, VM-entry controlfields, and VM-execution control fields in the VMCS. Care should be taken tomake sure the settings of individual fields match the allowed 0 and 1 settings forthe respective controls as reported by the VMX capability MSRs (see Appendix G).Any settings inconsistent with the settings reported by the capability MSRs willcause VM entries to fail.•Use VMWRITE to initialize various guest-state area fields in the working VMCS.This sets up the context and entry-point for guest execution upon VM entry.Chapter 22 describes the guest-state loading and checking done by the processorfor VM entries to protected and virtual-8086 guest execution.•The VMM is required to set up guest-state that complies with these consistencychecks:— If the VMM design requires the initial VM launch to cause guest software(typically the guest virtual BIOS) execution from the guest’s reset vector, itmay need to initialize the guest execution state to reflect the state of aphysical processor at power-on reset (described in Chapter 9, Intel® 64 andIA-32 Architectures Software Developer’s Manual, Volume 3A).— The VMM may need to initialize additional guest execution state that is notcaptured in the VMCS guest-state area by loading them directly on therespective processor registers.
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