Volume 3B System Programming Guide_ Part 2 (794104), страница 63
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There are considerationsthat impact VMM designs. These are described in the following subsections.25.9.1Operating Modes of Guest EnvironmentsFor Intel 64 processors, VMX operation supports host and guest environments thatrun in IA-32e mode or without IA-32e mode. VMX operation also supports host andguest environments on IA-32 processors.A VMM entering VMX operation while IA-32e mode is active is considered to be anIA-32e mode host.
A VMM entering VMX operation while IA-32e mode is not activated25-14 Vol. 3VIRTUAL-MACHINE MONITOR PROGRAMMING CONSIDERATIONSor not available is referred to as a 32-bit VMM. The type of guest operations suchVMMs support are summarized in Table 25-1.Table 25-1. Operating Modes for Host and Guest EnvironmentsCapabilityGuest Operationin IA-32e modeGuest OperationNot Requiring IA-32e ModeIA-32e mode VMMYesYes32-bit VMMNot supportedYesA VM exit may occur to an IA-32e mode guest in either 64-bit sub-mode or compatibility sub-mode of IA-32e mode.
VMMs may resume guests in either mode. The submode in which an IA-32e mode guest resumes VMX non-root operation is determinedby the attributes of the code segment which experienced the VM exit. If CS.L = 1,the guest is executing in 64-bit mode; if CS.L = 0, the guest is executing in compatibility mode (see Section 25.9.5).Not all of an IA-32e mode VMM must run in 64-bit mode.
While some parts of anIA-32e mode VMM must run in 64-bit mode, there are only a few restrictionspreventing a VMM from executing in compatibility mode. The most notable restrictionis that most VMX instructions cause exceptions when executed in compatibility mode.25.9.2Handling Widths of VMCS FieldsIndividual VMCS control fields must be accessed using VMREAD or VMWRITE instructions.
Outside of 64-Bit mode, VMREAD and VMWRITE operate on 32 bits of data. Thewidths of VMCS control fields may vary depending on whether a processor supportsIntel 64 architecture.Many VMCS fields are architected to extend transparently on processors supportingIntel 64 architecture (64 bits on processors that support Intel 64 architecture, 32 bitson processors that do not). Some VMCS fields are 64-bits wide regardless of whetherthe processor supports Intel 64 architecture or is in IA-32e mode.25.9.2.1Natural-Width VMCS FieldsMany VMCS fields operate using natural width. Such fields return (on reads) and set(on writes) 32-bits when operating in 32-bit mode and 64-bits when operating in64-bit mode.
For the most part, these fields return the naturally expected datawidths. The “Guest RIP” field in the VMCS guest-state area is an example of this typeof field.25.9.2.264-Bit VMCS FieldsUnlike natural width fields, these fields are fixed to 64-bit width on all processors.When in 64-bit mode, reads of these fields return 64-bit wide data and writes toVol. 3 25-15VIRTUAL-MACHINE MONITOR PROGRAMMING CONSIDERATIONSthese fields write 64-bits.
When outside of 64-bit mode, reads of these fields returnthe low 32-bits and writes to these fields write the low 32-bits and zero the upper32-bits. Should a non-IA-32e mode host require access to the upper 32-bits of thesefields, a separate VMCS encoding is used when issuing VMREAD/VMWRITE instructions.The VMCS control field “MSR bitmap address” (which contains the physical address ofa region of memory which specifies which MSR accesses should generate VM-exits) isan example of this type of field. Specifying encoding 00002004H to VMREAD returnsthe lower 32-bits to non-IA-32e mode hosts and returns 64-bits to 64-bit hosts. Theseparate encoding 00002005H returns only the upper 32-bits.25.9.3IA-32e Mode HostsAn IA-32e mode host is required to support 64-bit guest environments.
Because activating IA-32e mode currently requires that paging be disabled temporarily and VMXentry requires paging to be enabled, IA-32e mode must be enabled before enteringVMX operation. For this reason, it is not possible to toggle in and out of IA-32e modein a VMM.Section 25.5 describes the steps required to launch a VMM. An IA-32e mode host isalso required to set the “Host Address-Space Size” VMCS VM-exit control to 1. Thevalue of this control is then loaded in the IA32_EFER.LME/LMA and CS.L bits on eachVM exit. This establishes a 64-bit host environment as execution transfers to theVMM entry point. At a minimum, the entry point is required to be in a 64-bit codesegment. Subsequently, the VMM can, if it chooses, switch to 32-bit compatibilitymode on a code-segment basis (see Section 25.9.1).
Note, however, that VMXinstructions other than VMCALL are not supported in compatibility mode; theygenerate an invalid opcode exception if used.The following VMCS controls determine the value of IA32_EFER when a VM exitoccurs: the “Host Address-Space Size” control (described above), the “VM-exit MSRload count,” and the “VM-exit MSR-load address” (see Section 23.3).
The loading ofIA32_EFER.LME/LMA and CS.L bits established by the “Host Address-Space Size”control precede any loading of the IA32_EFER MSR due from the VM-exit MSR-loadarea. If IA32_EFER is specified in the VM-exit MSR-load area, the value of the LME bitin the load image of IA32_EFER should match the setting of the “Host Address-SpaceSize” control. Otherwise the attempt to modify the LME bit (while paging is enabled)will lead to a VMX-abort.On the other hand, the IA32_EFER.LMA bit is always set by the processor (determined by the value of the LME bit, the CR0.PG bit, and the CR4.PAE bit) regardless ofany value specified in the load image of the IA32_EFER MSR.
For these and performance reasons, VMM writers may choose to not use the VM-exit/entry MSRload/save areas for IA32_EFER.On a VMM teardown, VMX operation should be exited before deactivating IA-32emode if the latter is required.25-16 Vol. 3VIRTUAL-MACHINE MONITOR PROGRAMMING CONSIDERATIONS25.9.4IA-32e Mode GuestsA 32-bit guest can be launched by either IA-32e-mode hosts or non-IA-32e-modehosts. A 64-bit guests can only be launched by a IA-32e-mode host.In addition to the steps outlined in Section 25.6, VMM writers need to:•Set the “IA-32e-Mode Guest” VM-entry control to 1 in the VMCS to assureVM-entry (VMLAUNCH or VMRESUME) will establish a 64-bit (or 32-bitcompatible) guest operating environment.•Enable paging (CR0.PG) and PAE mode (CR4.PAE) to assure VM-entry to a 64-bitguest will succeed.•Ensure that the host to be in IA-32e mode (the IA32_EFER.LMA must be set to 1)and the setting of the VM-exit “Host Address-Space Size” control bit in the VMCSmust also be set to 1.If each of the above conditions holds true, then VM-entry will copy the value of theVM-entry “IA-32e-Mode Guest” control bit into the guests IA32_EFER.LME bit whichwill result in subsequent activation of IA-32e mode.
If any of the above conditions isfalse, the VM-entry will fail and load state from the host-state area of the workingVMCS as if a VM exit had occurred (see Section 22.7).The following VMCS controls determine the value of IA32_EFER on a VM entry: the“IA-32e-Mode Guest” VM-entry control (described above), the “VM-entry MSR-loadcount,” and the “VM-entry MSR-load address” (see Section 22.4).The loading of IA32_EFER.LME bit (described above) precedes any loading of theIA32_EFER MSR from the VM-entry MSR-load area of the VMCS. If loading ofIA32_EFER is specified in the VM-entry MSR-load area, the value of the LME bit in theload image should be match the setting of the “IA-32e-Mode Guest” VM-entrycontrol.
Otherwise, the attempt to modify the LME bit (while paging is enabled)results in a failed VM entry.On the other hand, the IA32_EFER.LMA bit is always set by the processor (determined by the value of the LME bit, the CR0.PG bit, and the CR4.PAE bit) regardless ofany value specified in the load image of IA32_EFER. For these and performancereasons, VMM writers may choose to not use the VM-exit/entry MSR-load/save areasfor IA32_EFER MSR.Note that the VMM can control the processor’s architectural state when transferringcontrol to a VM. VMM writers may choose to launch guests in protected mode andsubsequently allow the guest to activate IA-32e mode or they may allow guests totoggle in and out of IA-32e mode. In this case, the VMM should require VM exit onaccesses to the IA32_EFER MSR to detect changes in the operating mode and modifythe VM-entry “IA-32e-Mode Guest” control accordingly.A VMM should save/restore the extended (full 64-bit) contents of the guest generalpurpose registers, the new general-purpose registers (R8-R15) and the SIMD registers introduced in 64-bit mode should it need to modify these upon VM exit.Vol.
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