Volume 2A Instruction Set Reference A-M (794101), страница 98
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See the “IA-32 Architecture Compatibility” section below.The LOCK prefix can be prepended only to the following instructions and only to thoseforms of the instructions where the destination operand is a memory operand: ADD,ADC, AND, BTC, BTR, BTS, CMPXCHG, CMPXCH8B, DEC, INC, NEG, NOT, OR, SBB,SUB, XOR, XADD, and XCHG. If the LOCK prefix is used with one of these instructionsand the source operand is a memory operand, an undefined opcode exception (#UD)may be generated. An undefined opcode exception will also be generated if the LOCKprefix is used with any instruction not in the above list. The XCHG instruction alwaysasserts the LOCK# signal regardless of the presence or absence of the LOCK prefix.The LOCK prefix is typically used with the BTS instruction to perform a read-modifywrite operation on a memory location in shared memory environment.The integrity of the LOCK prefix is not affected by the alignment of the memory field.Memory locking is observed for arbitrarily misaligned fields.This instruction’s operation is the same in non-64-bit modes and 64-bit mode.IA-32 Architecture CompatibilityBeginning with the P6 family processors, when the LOCK prefix is prefixed to aninstruction and the memory area being accessed is cached internally in theprocessor, the LOCK# signal is generally not asserted.
Instead, only the processor’scache is locked. Here, the processor’s cache coherency mechanism ensures that the3-614 Vol. 2ALOCK—Assert LOCK# Signal PrefixINSTRUCTION SET REFERENCE, A-Moperation is carried out atomically with regards to memory. See “Effects of a LockedOperation on Internal Processor Caches” in Chapter 8 of Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 3A, the for more information onlocking of caches.OperationAssertLOCK#(DurationOfAccompaningInstruction);Flags AffectedNone.Protected Mode Exceptions#UDIf the LOCK prefix is used with an instruction not listed: ADD,ADC, AND, BTC, BTR, BTS, CMPXCHG, CMPXCH8B, DEC, INC,NEG, NOT, OR, SBB, SUB, XOR, XADD, XCHG.Other exceptions can be generated by the instruction when theLOCK prefix is applied.Real-Address Mode ExceptionsSame exceptions as in protected mode.Virtual-8086 Mode ExceptionsSame exceptions as in protected mode.Compatibility Mode ExceptionsSame exceptions as in protected mode.64-Bit Mode ExceptionsSame exceptions as in protected mode.LOCK—Assert LOCK# Signal PrefixVol.
2A 3-615INSTRUCTION SET REFERENCE, A-MLODS/LODSB/LODSW/LODSD/LODSQ—Load StringOpcodeInstructionOp/En64-BitModeCompat/ DescriptionLeg ModeACLODS m8AValidValidFor legacy mode, Load byteat address DS:(E)SI into AL.For 64-bit mode load byteat address (R)SI into AL.ADLODS m16AValidValidFor legacy mode, Load wordat address DS:(E)SI into AX.For 64-bit mode load wordat address (R)SI into AX.ADLODS m32AValidValidFor legacy mode, Loaddword at address DS:(E)SIinto EAX. For 64-bit modeload dword at address (R)SIinto EAX.REX.W + ADLODS m64AValidN.E.Load qword at address (R)SIinto RAX.ACLODSBAValidValidFor legacy mode, Load byteat address DS:(E)SI into AL.For 64-bit mode load byteat address (R)SI into AL.ADLODSWAValidValidFor legacy mode, Load wordat address DS:(E)SI into AX.For 64-bit mode load wordat address (R)SI into AX.ADLODSDAValidValidFor legacy mode, Loaddword at address DS:(E)SIinto EAX.
For 64-bit modeload dword at address (R)SIinto EAX.REX.W + ADLODSQAValidN.E.Load qword at address (R)SIinto RAX.Instruction Operand EncodingOp/EnOperand 1Operand 2Operand 3Operand 4ANANANANADescriptionLoads a byte, word, or doubleword from the source operand into the AL, AX, or EAXregister, respectively. The source operand is a memory location, the address of which3-616 Vol. 2ALODS/LODSB/LODSW/LODSD/LODSQ—Load StringINSTRUCTION SET REFERENCE, A-Mis read from the DS:EDI or the DS:SI registers (depending on the address-sizeattribute of the instruction, 32 or 16, respectively).
The DS segment may be overridden with a segment override prefix.At the assembly-code level, two forms of this instruction are allowed: the “explicitoperands” form and the “no-operands” form. The explicit-operands form (specifiedwith the LODS mnemonic) allows the source operand to be specified explicitly. Here,the source operand should be a symbol that indicates the size and location of thesource value.
The destination operand is then automatically selected to match thesize of the source operand (the AL register for byte operands, AX for word operands,and EAX for doubleword operands). This explicit-operands form is provided to allowdocumentation; however, note that the documentation provided by this form can bemisleading. That is, the source operand symbol must specify the correct type (size)of the operand (byte, word, or doubleword), but it does not have to specify thecorrect location. The location is always specified by the DS:(E)SI registers, whichmust be loaded correctly before the load string instruction is executed.The no-operands form provides “short forms” of the byte, word, and doublewordversions of the LODS instructions. Here also DS:(E)SI is assumed to be the sourceoperand and the AL, AX, or EAX register is assumed to be the destination operand.The size of the source and destination operands is selected with the mnemonic:LODSB (byte loaded into register AL), LODSW (word loaded into AX), or LODSD(doubleword loaded into EAX).After the byte, word, or doubleword is transferred from the memory location into theAL, AX, or EAX register, the (E)SI register is incremented or decremented automatically according to the setting of the DF flag in the EFLAGS register.
(If the DF flag is0, the (E)SI register is incremented; if the DF flag is 1, the ESI register is decremented.) The (E)SI register is incremented or decremented by 1 for byte operations,by 2 for word operations, or by 4 for doubleword operations.In 64-bit mode, use of the REX.W prefix promotes operation to 64 bits. LODS/LODSQload the quadword at address (R)SI into RAX. The (R)SI register is then incrementedor decremented automatically according to the setting of the DF flag in the EFLAGSregister.The LODS, LODSB, LODSW, and LODSD instructions can be preceded by the REPprefix for block loads of ECX bytes, words, or doublewords.
More often, however,these instructions are used within a LOOP construct because further processing ofthe data moved into the register is usually necessary before the next transfer can bemade. See “REP/REPE/REPZ /REPNE/REPNZ—Repeat String Operation Prefix” inChapter 4 of the Intel® 64 and IA-32 Architectures Software Developer’s Manual,Volume 2B, for a description of the REP prefix.OperationIF AL ← SRC; (* Byte load *)THEN AL ← SRC; (* Byte load *)IF DF = 0THEN (E)SI ← (E)SI + 1;LODS/LODSB/LODSW/LODSD/LODSQ—Load StringVol. 2A 3-617INSTRUCTION SET REFERENCE, A-MELSE (E)SI ← (E)SI – 1;FI;ELSE IF AX ← SRC; (* Word load *)THEN IF DF = 0THEN (E)SI ← (E)SI + 2;ELSE (E)SI ← (E)SI – 2;IF;FI;ELSE IF EAX ← SRC; (* Doubleword load *)THEN IF DF = 0THEN (E)SI ← (E)SI + 4;ELSE (E)SI ← (E)SI – 4;FI;FI;ELSE IF RAX ← SRC; (* Quadword load *)THEN IF DF = 0THEN (R)SI ← (R)SI + 8;ELSE (R)SI ← (R)SI – 8;FI;FI;FI;Flags AffectedNone.Protected Mode Exceptions#GP(0)If a memory operand effective address is outside the CS, DS,ES, FS, or GS segment limit.If the DS, ES, FS, or GS register contains a NULL segmentselector.#SS(0)If a memory operand effective address is outside the SSsegment limit.#PF(fault-code)If a page fault occurs.#AC(0)If alignment checking is enabled and an unaligned memoryreference is made while the current privilege level is 3.#UDIf the LOCK prefix is used.Real-Address Mode Exceptions#GPIf a memory operand effective address is outside the CS, DS,ES, FS, or GS segment limit.#SSIf a memory operand effective address is outside the SSsegment limit.3-618 Vol.
2ALODS/LODSB/LODSW/LODSD/LODSQ—Load StringINSTRUCTION SET REFERENCE, A-M#UDIf the LOCK prefix is used.Virtual-8086 Mode Exceptions#GP(0)If a memory operand effective address is outside the CS, DS,ES, FS, or GS segment limit.#SS(0)If a memory operand effective address is outside the SSsegment limit.#PF(fault-code)If a page fault occurs.#AC(0)If alignment checking is enabled and an unaligned memoryreference is made.#UDIf the LOCK prefix is used.Compatibility Mode ExceptionsSame exceptions as in protected mode.64-Bit Mode Exceptions#SS(0)If a memory address referencing the SS segment is in a noncanonical form.#GP(0)If the memory address is in a non-canonical form.#PF(fault-code)If a page fault occurs.#AC(0)If alignment checking is enabled and an unaligned memoryreference is made while the current privilege level is 3.#UDIf the LOCK prefix is used.LODS/LODSB/LODSW/LODSD/LODSQ—Load StringVol.
2A 3-619INSTRUCTION SET REFERENCE, A-MLOOP/LOOPcc—Loop According to ECX CounterOpcodeInstructionOp/En64-BitModeCompat/ DescriptionLeg ModeE2 cbLOOP rel8AValidValidDecrement count; jumpshort if count ≠ 0.E1 cbLOOPE rel8AValidValidDecrement count; jumpshort if count ≠ 0 and ZF =1.E0 cbLOOPNE rel8AValidValidDecrement count; jumpshort if count ≠ 0 and ZF =0.Instruction Operand EncodingOp/EnOperand 1Operand 2Operand 3Operand 4AOffsetNANANADescriptionPerforms a loop operation using the RCX, ECX or CX register as a counter (dependingon whether address size is 64 bits, 32 bits, or 16 bits). Note that the LOOP instructionignores REX.W; but 64-bit address size can be over-ridden using a 67H prefix.Each time the LOOP instruction is executed, the count register is decremented, thenchecked for 0. If the count is 0, the loop is terminated and program executioncontinues with the instruction following the LOOP instruction.
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