Volume 2A Instruction Set Reference A-M (794101), страница 93
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2AJMP—JumpINSTRUCTION SET REFERENCE, A-MIf the DPL from a call-gate, task-gate, or TSS segmentdescriptor is less than the CPL or than the RPL of the call-gate,task-gate, or TSS’s segment selector.If the segment descriptor for selector in a call gate does not indicate it is a code segment.If the segment descriptor for the segment selector in a task gatedoes not indicate an available TSS.If the segment selector for a TSS has its local/global bit set forlocal.If a TSS segment descriptor specifies that the TSS is busy or notavailable.#SS(0)#NP (selector)If a memory operand effective address is outside the SSsegment limit.If the code segment being accessed is not present.If call gate, task gate, or TSS not present.#PF(fault-code)If a page fault occurs.#AC(0)If alignment checking is enabled and an unaligned memoryreference is made while the current privilege level is 3.
(Onlyoccurs when fetching target from memory.)#UDIf the LOCK prefix is used.Real-Address Mode Exceptions#GPIf a memory operand effective address is outside the CS, DS,ES, FS, or GS segment limit.If a memory operand effective address is outside the CS, DS,ES, FS, or GS segment limit.#SSIf a memory operand effective address is outside the SSsegment limit.#UDIf the LOCK prefix is used.Virtual-8086 Mode Exceptions#GP(0)If the target operand is beyond the code segment limits.If a memory operand effective address is outside the CS, DS,ES, FS, or GS segment limit.#SS(0)If a memory operand effective address is outside the SSsegment limit.#PF(fault-code)If a page fault occurs.#AC(0)If alignment checking is enabled and an unaligned memoryreference is made.
(Only occurs when fetching target frommemory.)#UDIf the LOCK prefix is used.JMP—JumpVol. 2A 3-579INSTRUCTION SET REFERENCE, A-MCompatibility Mode ExceptionsSame as 64-bit mode exceptions.64-Bit Mode Exceptions#GP(0)If a memory address is non-canonical.If target offset in destination operand is non-canonical.If target offset in destination operand is beyond the new codesegment limit.If the segment selector in the destination operand is NULL.If the code segment selector in the 64-bit gate is NULL.#GP(selector)If the code segment or 64-bit call gate is outside descriptor tablelimits.If the code segment or 64-bit call gate overlaps non-canonicalspace.If the segment descriptor from a 64-bit call gate is in noncanonical space.If the segment descriptor pointed to by the segment selector inthe destination operand is not for a conforming-code segment,nonconforming-code segment, 64-bit call gate.If the segment descriptor pointed to by the segment selector inthe destination operand is a code segment, and has both theD-bit and the L-bit set.If the DPL for a nonconforming-code segment is not equal to theCPL, or the RPL for the segment’s segment selector is greaterthan the CPL.If the DPL for a conforming-code segment is greater than theCPL.If the DPL from a 64-bit call-gate is less than the CPL or than theRPL of the 64-bit call-gate.If the upper type field of a 64-bit call gate is not 0x0.If the segment selector from a 64-bit call gate is beyond thedescriptor table limits.If the code segment descriptor pointed to by the selector in the64-bit gate doesn't have the L-bit set and the D-bit clear.If the segment descriptor for a segment selector from the 64-bitcall gate does not indicate it is a code segment.If the code segment is non-confirming and CPL ≠ DPL.If the code segment is confirming and CPL < DPL.#NP(selector)If a code segment or 64-bit call gate is not present.#UD(64-bit mode only) If a far jump is direct to an absolute addressin memory.3-580 Vol.
2AJMP—JumpINSTRUCTION SET REFERENCE, A-MIf the LOCK prefix is used.#PF(fault-code)If a page fault occurs.#AC(0)If alignment checking is enabled and an unaligned memoryreference is made while the current privilege level is 3.JMP—JumpVol. 2A 3-581INSTRUCTION SET REFERENCE, A-MLAHF—Load Status Flags into AH RegisterOpcodeInstructionOp/En64-BitModeCompat/ DescriptionLeg Mode9FLAHFAInvalid*ValidLoad: AH ←EFLAGS(SF:ZF:0:AF:0:PF:1:CF).NOTES:*Valid in specific steppings. See Description section.Instruction Operand EncodingOp/EnOperand 1Operand 2Operand 3Operand 4ANANANANADescriptionThis instruction executes as described above in compatibility mode and legacy mode.It is valid in 64-bit mode only if CPUID.80000001H:ECX.LAHF-SAHF[bit 0] = 1.OperationIF 64-Bit ModeTHENIF CPUID.80000001H:ECX.LAHF-SAHF[bit 0] = 1;THEN AH ← RFLAGS(SF:ZF:0:AF:0:PF:1:CF);ELSE #UD;FI;ELSEAH ← EFLAGS(SF:ZF:0:AF:0:PF:1:CF);FI;Flags AffectedNone.
The state of the flags in the EFLAGS register is not affected.Protected Mode Exceptions#UDIf the LOCK prefix is used.Real-Address Mode ExceptionsSame exceptions as in protected mode.Virtual-8086 Mode ExceptionsSame exceptions as in protected mode.3-582 Vol. 2ALAHF—Load Status Flags into AH RegisterINSTRUCTION SET REFERENCE, A-MCompatibility Mode ExceptionsSame exceptions as in protected mode.64-Bit Mode Exceptions#UDIf CPUID.80000001H:ECX.LAHF-SAHF[bit 0] = 0.If the LOCK prefix is used.LAHF—Load Status Flags into AH RegisterVol. 2A 3-583INSTRUCTION SET REFERENCE, A-MLAR—Load Access Rights ByteOpcodeInstruction0F 02 /rOp/En64-BitModeCompat/ DescriptionLeg ModeLAR r16, r16/m16 AValidValidr16 ← r16/m16 masked byFF00H.0F 02 /rLAR r32,r32/m161AValidValidr32 ← r32/m16 masked by00FxFF00HREX.W + 0F 02/rLAR r64,r32/m161AValidN.E.r64 ← r32/m16 masked by00FxFF00H and zeroextendedNOTES:1.
For all loads (regardless of source or destination sizing) only bits 16-0 are used. Other bits areignored.Instruction Operand EncodingOp/EnOperand 1Operand 2Operand 3Operand 4AModRM:reg (w)ModRM:r/m (r)NANADescriptionLoads the access rights from the segment descriptor specified by the second operand(source operand) into the first operand (destination operand) and sets the ZF flag inthe flag register.
The source operand (which can be a register or a memory location)contains the segment selector for the segment descriptor being accessed. If thesource operand is a memory address, only 16 bits of data are accessed. The destination operand is a general-purpose register.The processor performs access checks as part of the loading process. Once loaded inthe destination register, software can perform additional checks on the access rightsinformation.When the operand size is 32 bits, the access rights for a segment descriptor includethe type and DPL fields and the S, P, AVL, D/B, and G flags, all of which are located inthe second doubleword (bytes 4 through 7) of the segment descriptor.
The doubleword is masked by 00FXFF00H before it is loaded into the destination operand. Whenthe operand size is 16 bits, the access rights include the type and DPL fields. Here,the two lower-order bytes of the doubleword are masked by FF00H before beingloaded into the destination operand.This instruction performs the following checks before it loads the access rights in thedestination register:••Checks that the segment selector is not NULL.Checks that the segment selector points to a descriptor that is within the limits ofthe GDT or LDT being accessed3-584 Vol.
2ALAR—Load Access Rights ByteINSTRUCTION SET REFERENCE, A-M•Checks that the descriptor type is valid for this instruction. All code and datasegment descriptors are valid for (can be accessed with) the LAR instruction. Thevalid system segment and gate descriptor types are given in Table 3-57.•If the segment is not a conforming code segment, it checks that the specifiedsegment descriptor is visible at the CPL (that is, if the CPL and the RPL of thesegment selector are less than or equal to the DPL of the segment selector).If the segment descriptor cannot be accessed or is an invalid type for the instruction,the ZF flag is cleared and no access rights are loaded in the destination operand.The LAR instruction can only be executed in protected mode and IA-32e mode.In 64-bit mode, the instruction’s default operation size is 32 bits.
Use of the REX.Wprefix permits access to 64-bit registers as destination.When the destination operand size is 64 bits, the access rights are loaded from thesecond doubleword (bytes 4 through 7) of the segment descriptor. The doubleword ismasked by 00FXFF00H and zero extended to 64 bits before it is loaded into the destination operand.Table 3-57. Segment and Gate TypesTypeProtected ModeNameIA-32e ModeValidNameValid0ReservedNoReservedNo1Available 16-bit TSSYesReservedNo2LDTYesLDTNo3Busy 16-bit TSSYesReservedNo416-bit call gateYesReservedNo516-bit/32-bit task gateYesReservedNo616-bit interrupt gateNoReservedNo716-bit trap gateNoReservedNo8ReservedNoReservedNo9Available 32-bit TSSYesAvailable 64-bit TSSYesAReservedNoReservedNoBBusy 32-bit TSSYesBusy 64-bit TSSYesC32-bit call gateYes64-bit call gateYesDReservedNoReservedNoE32-bit interrupt gateNo64-bit interrupt gateNoF32-bit trap gateNo64-bit trap gateNoLAR—Load Access Rights ByteVol.
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