Volume 2A Instruction Set Reference A-M (794101), страница 94
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2A 3-585INSTRUCTION SET REFERENCE, A-MOperationIF Offset(SRC) > descriptor table limitTHENZF = 0;ELSEIF SegmentDescriptor(Type) ≠ conforming code segmentand (CPL > DPL) or (RPL > DPL)or segment type is not valid for instructionTHENZF ← 0ELSETEMP ← Read segment descriptor ;IF OperandSize = 64THENDEST ← (ACCESSRIGHTWORD(TEMP) AND 00000000_00FxFF00H);ELSE (* OperandSize = 32*)DEST ← (ACCESSRIGHTWORD(TEMP) AND 00FxFF00H);ELSE (* OperandSize = 16 *)DEST ← (ACCESSRIGHTWORD(TEMP) AND FF00H);FI;FI;FI:Flags AffectedThe ZF flag is set to 1 if the access rights are loaded successfully; otherwise, it is setto 0.Protected Mode Exceptions#GP(0)If a memory operand effective address is outside the CS, DS,ES, FS, or GS segment limit.If the DS, ES, FS, or GS register is used to access memory and itcontains a NULL segment selector.#SS(0)If a memory operand effective address is outside the SSsegment limit.#PF(fault-code)If a page fault occurs.#AC(0)If alignment checking is enabled and the memory operand effective address is unaligned while the current privilege level is 3.#UDIf the LOCK prefix is used.3-586 Vol.
2ALAR—Load Access Rights ByteINSTRUCTION SET REFERENCE, A-MReal-Address Mode Exceptions#UDThe LAR instruction is not recognized in real-address mode.Virtual-8086 Mode Exceptions#UDThe LAR instruction cannot be executed in virtual-8086 mode.Compatibility Mode ExceptionsSame exceptions as in protected mode.64-Bit Mode Exceptions#SS(0)If the memory operand effective address referencing the SSsegment is in a non-canonical form.#GP(0)If the memory operand effective address is in a non-canonicalform.#PF(fault-code)If a page fault occurs.#AC(0)If alignment checking is enabled and the memory operand effective address is unaligned while the current privilege level is 3.#UDIf the LOCK prefix is used.LAR—Load Access Rights ByteVol.
2A 3-587INSTRUCTION SET REFERENCE, A-MLDDQU—Load Unaligned Integer 128 BitsOpcodeInstructionOp/En64-BitModeCompat/ DescriptionLeg ModeF2 0F F0 /rLDDQU xmm1,memAValidValidLoad unaligned data frommem and return doublequadword in xmm1.Instruction Operand EncodingOp/EnOperand 1Operand 2Operand 3Operand 4AModRM:reg (w)ModRM:r/m (r)NANADescriptionThe instruction is functionally similar to MOVDQU xmm, m128 for loading frommemory. That is: 16 bytes of data starting at an address specified by the sourcememory operand (second operand) are fetched from memory and placed in a destination register (first operand). The source operand need not be aligned on a 16-byteboundary.
Up to 32 bytes may be loaded from memory; this is implementationdependent.This instruction may improve performance relative to MOVDQU if the source operandcrosses a cache line boundary. In situations that require the data loaded by LDDQUbe modified and stored to the same location, use MOVDQU or MOVDQA instead ofLDDQU. To move a double quadword to or from memory locations that are known tobe aligned on 16-byte boundaries, use the MOVDQA instruction.Implementation Notes•If the source is aligned to a 16-byte boundary, based on the implementation, the16 bytes may be loaded more than once.
For that reason, the usage of LDDQUshould be avoided when using uncached or write-combining (WC) memoryregions. For uncached or WC memory regions, keep using MOVDQU.•This instruction is a replacement for MOVDQU (load) in situations where cacheline splits significantly affect performance. It should not be used in situationswhere store-load forwarding is performance critical. If performance of store-loadforwarding is critical to the application, use MOVDQA store-load pairs when datais 128-bit aligned or MOVDQU store-load pairs when data is 128-bit unaligned.•If the memory address is not aligned on 16-byte boundary, some implementations may load up to 32 bytes and return 16 bytes in the destination.
Someprocessor implementations may issue multiple loads to access the appropriate 16bytes. Developers of multi-threaded or multi-processor software should be awarethat on these processors the loads will be performed in a non-atomic way.In 64-bit mode, use of the REX.R prefix permits this instruction to access additionalregisters (XMM8-XMM15).3-588 Vol. 2ALDDQU—Load Unaligned Integer 128 BitsINSTRUCTION SET REFERENCE, A-MOperationxmm[127:0] = m128;Intel C/C++ Compiler Intrinsic EquivalentLDDQU__m128i _mm_lddqu_si128(__m128i const *p)Numeric ExceptionsNone.Protected Mode Exceptions#GP(0)For an illegal memory operand effective address in the CS, DS,ES, FS or GS segments.#SS(0)For an illegal address in the SS segment.#PF(fault-code)For a page fault.#NMIf CR0.TS[bit 3] = 1.#UDIf CR4.OSFXSR[bit 9] = 0.If CR0.EM[bit 2] = 1.If CPUID.01H:ECX.SSE3[bit 0] = 0.If the LOCK prefix is used.#AC(0)If alignment checking is enabled and an unaligned memoryreference is made while the current privilege level is 3.Real Address Mode ExceptionsGP(0)If any part of the operand would lie outside of the effectiveaddress space from 0 to 0FFFFH.#NMIf CR0.TS[bit 3] = 1.#UDIf CR0.EM[bit 2] = 1.If CR4.OSFXSR[bit 9] = 0.If CPUID.01H:ECX.SSE3[bit 0] = 0.If the LOCK prefix is used.Virtual 8086 Mode ExceptionsGP(0)If any part of the operand would lie outside of the effectiveaddress space from 0 to 0FFFFH.#NMIf CR0.TS[bit 3] = 1.#UDIf CR0.EM[bit 2] = 1.If CR4.OSFXSR[bit 9] = 0.If CPUID.01H:ECX.SSE3[bit 0] = 0.LDDQU—Load Unaligned Integer 128 BitsVol.
2A 3-589INSTRUCTION SET REFERENCE, A-MIf the LOCK prefix is used.#PF(fault-code)For a page fault.#AC(0)If alignment checking is enabled and an unaligned memoryreference is made.Compatibility Mode ExceptionsSame exceptions as in protected mode.64-Bit Mode Exceptions#SS(0)If a memory address referencing the SS segment is in a noncanonical form.#GP(0)If the memory address is in a non-canonical form.#NMIf CR0.TS[bit 3] = 1.#UDIf CR0.EM[bit 2] = 1.If CR4.OSFXSR[bit 9] = 0.If CPUID.01H:ECX.SSE3[bit 0] = 0.If the LOCK prefix is used.#PF(fault-code)3-590 Vol. 2AIf a page fault occurs.LDDQU—Load Unaligned Integer 128 BitsINSTRUCTION SET REFERENCE, A-MLDMXCSR—Load MXCSR RegisterOpcodeInstructionOp/En64-BitModeCompat/ DescriptionLeg Mode0F,AE,/2LDMXCSR m32AValidValidLoad MXCSR register fromm32.Instruction Operand EncodingOp/EnOperand 1Operand 2Operand 3Operand 4AModRM:r/m (r)NANANADescriptionLoads the source operand into the MXCSR control/status register.
The sourceoperand is a 32-bit memory location. See “MXCSR Control and Status Register” inChapter 10, of the Intel® 64 and IA-32 Architectures Software Developer’s Manual,Volume 1, for a description of the MXCSR register and its contents.The LDMXCSR instruction is typically used in conjunction with the STMXCSR instruction, which stores the contents of the MXCSR register in memory.The default MXCSR value at reset is 1F80H.If a LDMXCSR instruction clears a SIMD floating-point exception mask bit and setsthe corresponding exception flag bit, a SIMD floating-point exception will not beimmediately generated. The exception will be generated only upon the execution ofthe next SSE or SSE2 instruction that causes that particular SIMD floating-pointexception to be reported.This instruction’s operation is the same in non-64-bit modes and 64-bit mode.OperationMXCSR ← m32;C/C++ Compiler Intrinsic Equivalent_mm_setcsr(unsigned int i)Numeric ExceptionsNone.Protected Mode Exceptions#GP(0)For an illegal memory operand effective address in the CS, DS,ES, FS, or GS segments.For an attempt to set reserved bits in MXCSR.LDMXCSR—Load MXCSR RegisterVol.
2A 3-591INSTRUCTION SET REFERENCE, A-M#SS(0)For an illegal address in the SS segment.#PF(fault-code)For a page fault.#NMIf CR0.TS[bit 3] = 1.#UDIf CR0.EM[bit 2] = 1.If CR4.OSFXSR[bit 9] = 0.If CPUID.01H:EDX.SSE[bit 25] = 0.If the LOCK prefix is used.#AC(0)If alignment checking is enabled and an unaligned memoryreference is made while the current privilege level is 3.Real Address Mode ExceptionsGP(0)If any part of the operand would lie outside of the effectiveaddress space from 0 to FFFFH.#NMIf CR0.TS[bit 3] = 1.#UDIf CR0.EM[bit 2] = 1.For an attempt to set reserved bits in MXCSR.If CR4.OSFXSR[bit 9] = 0.If CPUID.01H:EDX.SSE[bit 25] = 0.If the LOCK prefix is used.Virtual 8086 Mode ExceptionsSame exceptions as in real address mode.#PF(fault-code)For a page fault.#AC(0)If alignment checking is enabled and an unaligned memoryreference is made.If the LOCK prefix is used.Compatibility Mode ExceptionsSame exceptions as in protected mode.64-Bit Mode Exceptions#SS(0)If a memory address referencing the SS segment is in a noncanonical form.#GP(0)If the memory address is in a non-canonical form.For an attempt to set reserved bits in MXCSR.#PF(fault-code)For a page fault.#NMIf CR0.TS[bit 3] = 1.#UDIf CR0.EM[bit 2] = 1.If CR4.OSFXSR[bit 9] = 0.3-592 Vol.
2ALDMXCSR—Load MXCSR RegisterINSTRUCTION SET REFERENCE, A-MIf CPUID.01H:EDX.SSE[bit 25] = 0.If the LOCK prefix is used.#AC(0)If alignment checking is enabled and an unaligned memoryreference is made while the current privilege level is 3.LDMXCSR—Load MXCSR RegisterVol. 2A 3-593INSTRUCTION SET REFERENCE, A-MLDS/LES/LFS/LGS/LSS—Load Far PointerOpcodeInstructionOp/En64-BitModeCompat/ DescriptionLeg ModeC5 /rLDS r16,m16:16AInvalidValidLoad DS:r16 with far pointerfrom memory.C5 /rLDS r32,m16:32AInvalidValidLoad DS:r32 with far pointerfrom memory.0F B2 /rLSS r16,m16:16AValidValidLoad SS:r16 with far pointerfrom memory.0F B2 /rLSS r32,m16:32AValidValidLoad SS:r32 with far pointerfrom memory.REX + 0F B2 /rLSS r64,m16:64AValidN.E.Load SS:r64 with far pointerfrom memory.C4 /rLES r16,m16:16AInvalidValidLoad ES:r16 with far pointerfrom memory.C4 /rLES r32,m16:32AInvalidValidLoad ES:r32 with far pointerfrom memory.0F B4 /rLFS r16,m16:16AValidValidLoad FS:r16 with far pointerfrom memory.0F B4 /rLFS r32,m16:32AValidValidLoad FS:r32 with far pointerfrom memory.REX + 0F B4 /rLFS r64,m16:64AValidN.E.Load FS:r64 with far pointerfrom memory.0F B5 /rLGS r16,m16:16AValidValidLoad GS:r16 with far pointerfrom memory.0F B5 /rLGS r32,m16:32AValidValidLoad GS:r32 with far pointerfrom memory.REX + 0F B5 /rLGS r64,m16:64AValidN.E.Load GS:r64 with far pointerfrom memory.Instruction Operand EncodingOp/EnOperand 1Operand 2Operand 3Operand 4AModRM:reg (w)ModRM:r/m (r)NANADescriptionLoads a far pointer (segment selector and offset) from the second operand (sourceoperand) into a segment register and the first operand (destination operand).
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