Volume 2A Instruction Set Reference A-M (794101), страница 97
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They are the only instructions that directly load alinear address (that is, not a segment-relative address) and a limit in protectedmode. They are commonly executed in real-address mode to allow processor initialization prior to switching to protected mode.In 64-bit mode, the instruction’s operand size is fixed at 8+2 bytes (an 8-byte baseand a 2-byte limit). See the summary chart at the beginning of this section forencoding data and limits.See “SGDT—Store Global Descriptor Table Register” in Chapter 4, Intel® 64 andIA-32 Architectures Software Developer’s Manual, Volume 2B, for information onstoring the contents of the GDTR and IDTR.OperationIF Instruction is LIDTTHENIF OperandSize = 16THEN3-606 Vol. 2ALGDT/LIDT—Load Global/Interrupt Descriptor Table RegisterINSTRUCTION SET REFERENCE, A-MIDTR(Limit) ← SRC[0:15];IDTR(Base) ← SRC[16:47] AND 00FFFFFFH;ELSE IF 32-bit Operand SizeTHENIDTR(Limit) ← SRC[0:15];IDTR(Base) ← SRC[16:47];FI;ELSE IF 64-bit Operand Size (* In 64-Bit Mode *)THENIDTR(Limit) ← SRC[0:15];IDTR(Base) ← SRC[16:79];FI;FI;ELSE (* Instruction is LGDT *)IF OperandSize = 16THENGDTR(Limit) ← SRC[0:15];GDTR(Base) ← SRC[16:47] AND 00FFFFFFH;ELSE IF 32-bit Operand SizeTHENGDTR(Limit) ← SRC[0:15];GDTR(Base) ← SRC[16:47];FI;ELSE IF 64-bit Operand Size (* In 64-Bit Mode *)THENGDTR(Limit) ← SRC[0:15];GDTR(Base) ← SRC[16:79];FI;FI;FI;Flags AffectedNone.Protected Mode Exceptions#UDIf source operand is not a memory location.#GP(0)If the current privilege level is not 0.If the LOCK prefix is used.If a memory operand effective address is outside the CS, DS,ES, FS, or GS segment limit.If the DS, ES, FS, or GS register is used to access memory and itcontains a NULL segment selector.LGDT/LIDT—Load Global/Interrupt Descriptor Table RegisterVol.
2A 3-607INSTRUCTION SET REFERENCE, A-M#SS(0)If a memory operand effective address is outside the SSsegment limit.#PF(fault-code)If a page fault occurs.Real-Address Mode Exceptions#UDIf source operand is not a memory location.If the LOCK prefix is used.#GPIf a memory operand effective address is outside the CS, DS,ES, FS, or GS segment limit.#SSIf a memory operand effective address is outside the SSsegment limit.Virtual-8086 Mode Exceptions#UDIf source operand is not a memory location.If the LOCK prefix is used.#GP(0)The LGDT and LIDT instructions are not recognized in virtual8086 mode.#GPIf the current privilege level is not 0.Compatibility Mode ExceptionsSame exceptions as in protected mode.64-Bit Mode Exceptions#SS(0)If a memory address referencing the SS segment is in a noncanonical form.#GP(0)If the current privilege level is not 0.#UDIf source operand is not a memory location.#PF(fault-code)If a page fault occurs.If the memory address is in a non-canonical form.If the LOCK prefix is used.3-608 Vol.
2ALGDT/LIDT—Load Global/Interrupt Descriptor Table RegisterINSTRUCTION SET REFERENCE, A-MLLDT—Load Local Descriptor Table RegisterOpcodeInstructionOp/En64-BitModeCompat/ DescriptionLeg Mode0F 00 /2LLDT r/m16AValidValidLoad segment selectorr/m16 into LDTR.Instruction Operand EncodingOp/EnOperand 1Operand 2Operand 3Operand 4AModRM:r/m (r)NANANADescriptionLoads the source operand into the segment selector field of the local descriptor tableregister (LDTR).
The source operand (a general-purpose register or a memory location) contains a segment selector that points to a local descriptor table (LDT). Afterthe segment selector is loaded in the LDTR, the processor uses the segment selectorto locate the segment descriptor for the LDT in the global descriptor table (GDT). Itthen loads the segment limit and base address for the LDT from the segmentdescriptor into the LDTR. The segment registers DS, ES, SS, FS, GS, and CS are notaffected by this instruction, nor is the LDTR field in the task state segment (TSS) forthe current task.If bits 2-15 of the source operand are 0, LDTR is marked invalid and the LLDT instruction completes silently.
However, all subsequent references to descriptors in the LDT(except by the LAR, VERR, VERW or LSL instructions) cause a general protectionexception (#GP).The operand-size attribute has no effect on this instruction.The LLDT instruction is provided for use in operating-system software; it should notbe used in application programs. This instruction can only be executed in protectedmode or 64-bit mode.In 64-bit mode, the operand size is fixed at 16 bits.OperationIF SRC(Offset) > descriptor table limitTHEN #GP(segment selector); FI;IF segment selector is validRead segment descriptor;IF SegmentDescriptor(Type) ≠ LDTTHEN #GP(segment selector); FI;LLDT—Load Local Descriptor Table RegisterVol.
2A 3-609INSTRUCTION SET REFERENCE, A-MIF segment descriptor is not presentTHEN #NP(segment selector); FI;LDTR(SegmentSelector) ← SRC;LDTR(SegmentDescriptor) ← GDTSegmentDescriptor;ELSE LDTR ← INVALIDFI;Flags AffectedNone.Protected Mode Exceptions#GP(0)If the current privilege level is not 0.If a memory operand effective address is outside the CS, DS,ES, FS, or GS segment limit.If the DS, ES, FS, or GS register contains a NULL segmentselector.#GP(selector)If the selector operand does not point into the Global DescriptorTable or if the entry in the GDT is not a Local Descriptor Table.Segment selector is beyond GDT limit.#SS(0)If a memory operand effective address is outside the SSsegment limit.#NP(selector)If the LDT descriptor is not present.#PF(fault-code)If a page fault occurs.#UDIf the LOCK prefix is used.Real-Address Mode Exceptions#UDThe LLDT instruction is not recognized in real-address mode.Virtual-8086 Mode Exceptions#UDThe LLDT instruction is not recognized in virtual-8086 mode.Compatibility Mode ExceptionsSame exceptions as in protected mode.64-Bit Mode Exceptions#SS(0)If a memory address referencing the SS segment is in a noncanonical form.#GP(0)If the current privilege level is not 0.If the memory address is in a non-canonical form.3-610 Vol.
2ALLDT—Load Local Descriptor Table RegisterINSTRUCTION SET REFERENCE, A-M#GP(selector)If the selector operand does not point into the Global DescriptorTable or if the entry in the GDT is not a Local Descriptor Table.#NP(selector)If the LDT descriptor is not present.#PF(fault-code)If a page fault occurs.#UDIf the LOCK prefix is used.Segment selector is beyond GDT limit.LLDT—Load Local Descriptor Table RegisterVol.
2A 3-611INSTRUCTION SET REFERENCE, A-MLMSW—Load Machine Status WordOpcodeInstructionOp/En64-BitModeCompat/ DescriptionLeg Mode0F 01 /6LMSW r/m16AValidValidLoads r/m16 in machinestatus word of CR0.Instruction Operand EncodingOp/EnOperand 1Operand 2Operand 3Operand 4AModRM:r/m (r)NANANADescriptionLoads the source operand into the machine status word, bits 0 through 15 of registerCR0. The source operand can be a 16-bit general-purpose register or a memory location.
Only the low-order 4 bits of the source operand (which contains the PE, MP, EM,and TS flags) are loaded into CR0. The PG, CD, NW, AM, WP, NE, and ET flags of CR0are not affected. The operand-size attribute has no effect on this instruction.If the PE flag of the source operand (bit 0) is set to 1, the instruction causes theprocessor to switch to protected mode. While in protected mode, the LMSW instruction cannot be used to clear the PE flag and force a switch back to real-address mode.The LMSW instruction is provided for use in operating-system software; it should notbe used in application programs. In protected or virtual-8086 mode, it can only beexecuted at CPL 0.This instruction is provided for compatibility with the Intel 286 processor; programsand procedures intended to run on the Pentium 4, Intel Xeon, P6 family, Pentium,Intel486, and Intel386 processors should use the MOV (control registers) instructionto load the whole CR0 register.
The MOV CR0 instruction can be used to set and clearthe PE flag in CR0, allowing a procedure or program to switch between protected andreal-address modes.This instruction is a serializing instruction.This instruction’s operation is the same in non-64-bit modes and 64-bit mode. Notethat the operand size is fixed at 16 bits.See “Changes to Instruction Behavior in VMX Non-Root Operation” in Chapter 22 ofthe Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 3B, formore information about the behavior of this instruction in VMX non-root operation.OperationCR0[0:3] ← SRC[0:3];3-612 Vol. 2ALMSW—Load Machine Status WordINSTRUCTION SET REFERENCE, A-MFlags AffectedNone.Protected Mode Exceptions#GP(0)If the current privilege level is not 0.If a memory operand effective address is outside the CS, DS,ES, FS, or GS segment limit.If the DS, ES, FS, or GS register is used to access memory and itcontains a NULL segment selector.#SS(0)If a memory operand effective address is outside the SSsegment limit.#PF(fault-code)If a page fault occurs.#UDIf the LOCK prefix is used.Real-Address Mode Exceptions#GPIf a memory operand effective address is outside the CS, DS,ES, FS, or GS segment limit.#UDIf the LOCK prefix is used.Virtual-8086 Mode Exceptions#GP(0)If a memory operand effective address is outside the CS, DS,ES, FS, or GS segment limit.#SS(0)If a memory operand effective address is outside the SSsegment limit.#PF(fault-code)If a page fault occurs.#UDIf the LOCK prefix is used.Compatibility Mode ExceptionsSame exceptions as in protected mode.64-Bit Mode Exceptions#SS(0)If a memory address referencing the SS segment is in a noncanonical form.#GP(0)If the current privilege level is not 0.#PF(fault-code)If a page fault occurs.#UDIf the LOCK prefix is used.If the memory address is in a non-canonical form.LMSW—Load Machine Status WordVol.
2A 3-613INSTRUCTION SET REFERENCE, A-MLOCK—Assert LOCK# Signal PrefixOpcodeInstructionOp/En64-BitModeCompat/ DescriptionLeg ModeF0LOCKAValidValidAsserts LOCK# signal forduration of theaccompanying instruction.NOTES:* See IA-32 Architecture Compatibility section below.Instruction Operand EncodingOp/EnOperand 1Operand 2Operand 3Operand 4ANANANANADescriptionCauses the processor’s LOCK# signal to be asserted during execution of the accompanying instruction (turns the instruction into an atomic instruction). In a multiprocessor environment, the LOCK# signal ensures that the processor has exclusive useof any shared memory while the signal is asserted.Note that, in later Intel 64 and IA-32 processors (including the Pentium 4, Intel Xeon,and P6 family processors), locking may occur without the LOCK# signal beingasserted.
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