Volume 2A Instruction Set Reference A-M (794101), страница 99
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If the count is not zero,a near jump is performed to the destination (target) operand, which is presumablythe instruction at the beginning of the loop.The target instruction is specified with a relative offset (a signed offset relative to thecurrent value of the instruction pointer in the IP/EIP/RIP register).
This offset isgenerally specified as a label in assembly code, but at the machine code level, it isencoded as a signed, 8-bit immediate value, which is added to the instruction pointer.Offsets of –128 to +127 are allowed with this instruction.Some forms of the loop instruction (LOOPcc) also accept the ZF flag as a condition forterminating the loop before the count reaches zero. With these forms of the instruction, a condition code (cc) is associated with each instruction to indicate the conditionbeing tested for. Here, the LOOPcc instruction itself does not affect the state of the ZFflag; the ZF flag is changed by other instructions in the loop.3-620 Vol. 2ALOOP/LOOPcc—Loop According to ECX CounterINSTRUCTION SET REFERENCE, A-MOperationIF (AddressSize = 32)THEN Count is ECX;ELSE IF (AddressSize = 64)Count is RCX;ELSE Count is CX;FI;Count ← Count – 1;IF Instruction is not LOOPTHENIF (Instruction ← LOOPE) or (Instruction ← LOOPZ)THEN IF (ZF = 1) and (Count ≠ 0)THEN BranchCond ← 1;ELSE BranchCond ← 0;FI;ELSE (Instruction = LOOPNE) or (Instruction = LOOPNZ)IF (ZF = 0 ) and (Count ≠ 0)THEN BranchCond ← 1;ELSE BranchCond ← 0;FI;FI;ELSE (* Instruction = LOOP *)IF (Count ≠ 0)THEN BranchCond ← 1;ELSE BranchCond ← 0;FI;FI;IF BranchCond = 1THENIF OperandSize = 32THEN EIP ← EIP + SignExtend(DEST);ELSE IF OperandSize = 64THEN RIP ← RIP + SignExtend(DEST);FI;ELSE IF OperandSize = 16THEN EIP ← EIP AND 0000FFFFH;FI;ELSE IF OperandSize = (32 or 64)THEN IF (R/E)IP < CS.Base or (R/E)IP > CS.Limit#GP; FI;FI;LOOP/LOOPcc—Loop According to ECX CounterVol.
2A 3-621INSTRUCTION SET REFERENCE, A-MFI;ELSETerminate loop and continue program execution at (R/E)IP;FI;Flags AffectedNone.Protected Mode Exceptions#GP(0)If the offset being jumped to is beyond the limits of the CSsegment.#UDIf the LOCK prefix is used.Real-Address Mode Exceptions#GPIf the offset being jumped to is beyond the limits of the CSsegment or is outside of the effective address space from 0 toFFFFH. This condition can occur if a 32-bit address size overrideprefix is used.#UDIf the LOCK prefix is used.Virtual-8086 Mode ExceptionsSame exceptions as in real address mode.Compatibility Mode ExceptionsSame exceptions as in protected mode.64-Bit Mode Exceptions#GP(0)If the offset being jumped to is in a non-canonical form.#UDIf the LOCK prefix is used.3-622 Vol. 2ALOOP/LOOPcc—Loop According to ECX CounterINSTRUCTION SET REFERENCE, A-MLSL—Load Segment LimitOpcodeInstructionOp/En64-BitModeCompat/ DescriptionLeg Mode0F 03 /rLSL r16, r16/m16AValidValidLoad: r16 ← segment limit,selector r16/m16.0F 03 /rLSL r32, r32/m16* AValidValidLoad: r32 ← segment limit,selector r32/m16.REX.W + 0F 03/rLSL r64, r32/m16* AValidValidLoad: r64 ← segment limit,selector r32/m16NOTES:* For all loads (regardless of destination sizing), only bits 16-0 are used.
Other bits are ignored.Instruction Operand EncodingOp/EnOperand 1Operand 2Operand 3Operand 4AModRM:reg (w)ModRM:r/m (r)NANADescriptionLoads the unscrambled segment limit from the segment descriptor specified with thesecond operand (source operand) into the first operand (destination operand) andsets the ZF flag in the EFLAGS register.
The source operand (which can be a registeror a memory location) contains the segment selector for the segment descriptorbeing accessed. The destination operand is a general-purpose register.The processor performs access checks as part of the loading process. Once loaded inthe destination register, software can compare the segment limit with the offset of apointer.The segment limit is a 20-bit value contained in bytes 0 and 1 and in the first 4 bitsof byte 6 of the segment descriptor.
If the descriptor has a byte granular segmentlimit (the granularity flag is set to 0), the destination operand is loaded with a bytegranular value (byte limit). If the descriptor has a page granular segment limit (thegranularity flag is set to 1), the LSL instruction will translate the page granular limit(page limit) into a byte limit before loading it into the destination operand. The translation is performed by shifting the 20-bit “raw” limit left 12 bits and filling the loworder 12 bits with 1s.When the operand size is 32 bits, the 32-bit byte limit is stored in the destinationoperand. When the operand size is 16 bits, a valid 32-bit limit is computed; however,the upper 16 bits are truncated and only the low-order 16 bits are loaded into thedestination operand.This instruction performs the following checks before it loads the segment limit intothe destination register:•Checks that the segment selector is not NULL.LSL—Load Segment LimitVol.
2A 3-623INSTRUCTION SET REFERENCE, A-M•Checks that the segment selector points to a descriptor that is within the limits ofthe GDT or LDT being accessed•Checks that the descriptor type is valid for this instruction. All code and datasegment descriptors are valid for (can be accessed with) the LSL instruction.
Thevalid special segment and gate descriptor types are given in the following table.•If the segment is not a conforming code segment, the instruction checks that thespecified segment descriptor is visible at the CPL (that is, if the CPL and the RPLof the segment selector are less than or equal to the DPL of the segmentselector).If the segment descriptor cannot be accessed or is an invalid type for the instruction,the ZF flag is cleared and no value is loaded in the destination operand.Table 3-60. Segment and Gate Descriptor TypesTypeProtected ModeNameIA-32e ModeValidNameValid0ReservedNoUpper 8 byte of a 16Byte descriptorYes1Available 16-bit TSSYesReservedNo2LDTYesLDTYes3Busy 16-bit TSSYesReservedNo416-bit call gateNoReservedNo516-bit/32-bit taskgateNoReservedNo616-bit interrupt gateNoReservedNo716-bit trap gateNoReservedNo8ReservedNoReservedNo9Available 32-bit TSSYes64-bit TSSYesAReservedNoReservedNoBBusy 32-bit TSSYesBusy 64-bit TSSYesC32-bit call gateNo64-bit call gateNoDReservedNoReservedNoE32-bit interrupt gateNo64-bit interrupt gateNoF32-bit trap gateNo64-bit trap gateNo3-624 Vol.
2ALSL—Load Segment LimitINSTRUCTION SET REFERENCE, A-MOperationIF SRC(Offset) > descriptor table limitTHEN ZF ← 0; FI;Read segment descriptor;IF SegmentDescriptor(Type) ≠ conforming code segmentand (CPL > DPL) OR (RPL > DPL)or Segment type is not valid for instructionTHENZF ← 0;ELSEtemp ← SegmentLimit([SRC]);IF (G ← 1)THEN temp ← ShiftLeft(12, temp) OR 00000FFFH;ELSE IF OperandSize = 32THEN DEST ← temp; FI;ELSE IF OperandSize = 64 (* REX.W used *)THEN DEST (* Zero-extended *) ← temp; FI;ELSE (* OperandSize = 16 *)DEST ← temp AND FFFFH;FI;FI;Flags AffectedThe ZF flag is set to 1 if the segment limit is loaded successfully; otherwise, it is setto 0.Protected Mode Exceptions#GP(0)If a memory operand effective address is outside the CS, DS,ES, FS, or GS segment limit.If the DS, ES, FS, or GS register is used to access memory and itcontains a NULL segment selector.#SS(0)If a memory operand effective address is outside the SSsegment limit.#PF(fault-code)If a page fault occurs.#AC(0)If alignment checking is enabled and the memory operand effective address is unaligned while the current privilege level is 3.#UDIf the LOCK prefix is used.Real-Address Mode Exceptions#UDLSL—Load Segment LimitThe LAR instruction cannot be executed in real-address mode.Vol.
2A 3-625INSTRUCTION SET REFERENCE, A-MVirtual-8086 Mode Exceptions#UDThe LAR instruction cannot be executed in virtual-8086 mode.Compatibility Mode ExceptionsSame exceptions as in protected mode.64-Bit Mode Exceptions#SS(0)If the memory operand effective address referencing the SSsegment is in a non-canonical form.#GP(0)If the memory operand effective address is in a non-canonicalform.#PF(fault-code)If a page fault occurs.#AC(0)If alignment checking is enabled and the memory operand effective address is unaligned while the current privilege level is 3.#UDIf the LOCK prefix is used.3-626 Vol. 2ALSL—Load Segment LimitINSTRUCTION SET REFERENCE, A-MLTR—Load Task RegisterOpcodeInstructionOp/En64-BitModeCompat/ DescriptionLeg Mode0F 00 /3LTR r/m16AValidValidLoad r/m16 into taskregister.Instruction Operand EncodingOp/EnOperand 1Operand 2Operand 3Operand 4AModRM:r/m (r)NANANADescriptionLoads the source operand into the segment selector field of the task register.
Thesource operand (a general-purpose register or a memory location) contains asegment selector that points to a task state segment (TSS). After the segmentselector is loaded in the task register, the processor uses the segment selector tolocate the segment descriptor for the TSS in the global descriptor table (GDT). It thenloads the segment limit and base address for the TSS from the segment descriptorinto the task register. The task pointed to by the task register is marked busy, but aswitch to the task does not occur.The LTR instruction is provided for use in operating-system software; it should not beused in application programs. It can only be executed in protected mode when theCPL is 0.
It is commonly used in initialization code to establish the first task to beexecuted.The operand-size attribute has no effect on this instruction.In 64-bit mode, the operand size is still fixed at 16 bits. The instruction references a16-byte descriptor to load the 64-bit base.OperationIF SRC is a NULL selectorTHEN #GP(0);IF SRC(Offset) > descriptor table limit OR IF SRC(type) ≠ globalTHEN #GP(segment selector); FI;Read segment descriptor;IF segment descriptor is not for an available TSSTHEN #GP(segment selector); FI;IF segment descriptor is not presentTHEN #NP(segment selector); FI;LTR—Load Task RegisterVol. 2A 3-627INSTRUCTION SET REFERENCE, A-MTSSsegmentDescriptor(busy) ← 1;(* Locked read-modify-write operation on the entire descriptor when setting busy flag *)TaskRegister(SegmentSelector) ← SRC;TaskRegister(SegmentDescriptor) ← TSSSegmentDescriptor;Flags AffectedNone.Protected Mode Exceptions#GP(0)If the current privilege level is not 0.If a memory operand effective address is outside the CS, DS,ES, FS, or GS segment limit.If the source operand contains a NULL segment selector.If the DS, ES, FS, or GS register is used to access memory and itcontains a NULL segment selector.#GP(selector)If the source selector points to a segment that is not a TSS or toone for a task that is already busy.#NP(selector)If the TSS is marked not present.#SS(0)If a memory operand effective address is outside the SSsegment limit.#PF(fault-code)If a page fault occurs.#UDIf the LOCK prefix is used.If the selector points to LDT or is beyond the GDT limit.Real-Address Mode Exceptions#UDThe LTR instruction is not recognized in real-address mode.Virtual-8086 Mode Exceptions#UDThe LTR instruction is not recognized in virtual-8086 mode.Compatibility Mode ExceptionsSame exceptions as in protected mode.64-Bit Mode Exceptions#SS(0)If a memory address referencing the SS segment is in a noncanonical form.#GP(0)If the current privilege level is not 0.If the memory address is in a non-canonical form.If the source operand contains a NULL segment selector.3-628 Vol.
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