Volume 2A Instruction Set Reference A-M (794101), страница 96
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The operand-size attribute of the instruction is determined by the chosenregister; the address-size attribute is determined by the attribute of the codesegment.Table 3-58. Non-64-bit Mode LEA Operation with Address and Operand SizeAttributesOperand SizeAddress SizeAction Performed161616-bit effective address is calculated and stored inrequested 16-bit register destination.163232-bit effective address is calculated. The lower 16 bits ofthe address are stored in the requested 16-bit registerdestination.321616-bit effective address is calculated. The 16-bit address iszero-extended and stored in the requested 32-bit registerdestination.323232-bit effective address is calculated and stored in therequested 32-bit register destination.Different assemblers may use different algorithms based on the size attribute andsymbolic reference of the source operand.3-600 Vol.
2ALEA—Load Effective AddressINSTRUCTION SET REFERENCE, A-MIn 64-bit mode, the instruction’s destination operand is governed by operand sizeattribute, the default operand size is 32 bits. Address calculation is governed byaddress size attribute, the default address size is 64-bits. In 64-bit mode, addresssize of 16 bits is not encodable. See Table 3-59.Table 3-59. 64-bit Mode LEA Operation with Address and Operand Size AttributesOperand SizeAddress SizeAction Performed163232-bit effective address is calculated (using 67H prefix). Thelower 16 bits of the address are stored in the requested16-bit register destination (using 66H prefix).166464-bit effective address is calculated (default address size).The lower 16 bits of the address are stored in the requested16-bit register destination (using 66H prefix).323232-bit effective address is calculated (using 67H prefix) andstored in the requested 32-bit register destination.326464-bit effective address is calculated (default address size)and the lower 32 bits of the address are stored in therequested 32-bit register destination.643232-bit effective address is calculated (using 67H prefix),zero-extended to 64-bits, and stored in the requested 64bit register destination (using REX.W).646464-bit effective address is calculated (default address size)and all 64-bits of the address are stored in the requested64-bit register destination (using REX.W).OperationIF OperandSize = 16 and AddressSize = 16THENDEST ← EffectiveAddress(SRC); (* 16-bit address *)ELSE IF OperandSize = 16 and AddressSize = 32THENtemp ← EffectiveAddress(SRC); (* 32-bit address *)DEST ← temp[0:15]; (* 16-bit address *)FI;ELSE IF OperandSize = 32 and AddressSize = 16THENtemp ← EffectiveAddress(SRC); (* 16-bit address *)DEST ← ZeroExtend(temp); (* 32-bit address *)FI;ELSE IF OperandSize = 32 and AddressSize = 32THENDEST ← EffectiveAddress(SRC); (* 32-bit address *)LEA—Load Effective AddressVol.
2A 3-601INSTRUCTION SET REFERENCE, A-MFI;ELSE IF OperandSize = 16 and AddressSize = 64THENtemp ← EffectiveAddress(SRC); (* 64-bit address *)DEST ← temp[0:15]; (* 16-bit address *)FI;ELSE IF OperandSize = 32 and AddressSize = 64THENtemp ← EffectiveAddress(SRC); (* 64-bit address *)DEST ← temp[0:31]; (* 16-bit address *)FI;ELSE IF OperandSize = 64 and AddressSize = 64THENDEST ← EffectiveAddress(SRC); (* 64-bit address *)FI;FI;Flags AffectedNone.Protected Mode Exceptions#UDIf source operand is not a memory location.If the LOCK prefix is used.Real-Address Mode ExceptionsSame exceptions as in protected mode.Virtual-8086 Mode ExceptionsSame exceptions as in protected mode.Compatibility Mode ExceptionsSame exceptions as in protected mode.64-Bit Mode ExceptionsSame exceptions as in protected mode.3-602 Vol.
2ALEA—Load Effective AddressINSTRUCTION SET REFERENCE, A-MLEAVE—High Level Procedure ExitOpcodeInstructionOp/En64-BitModeCompat/ DescriptionLeg ModeC9LEAVEAValidValidSet SP to BP, then pop BP.C9LEAVEAN.E.ValidSet ESP to EBP, then popEBP.C9LEAVEAValidN.E.Set RSP to RBP, then popRBP.Instruction Operand EncodingOp/EnOperand 1Operand 2Operand 3Operand 4ANANANANADescriptionReleases the stack frame set up by an earlier ENTER instruction. The LEAVE instruction copies the frame pointer (in the EBP register) into the stack pointer register(ESP), which releases the stack space allocated to the stack frame.
The old framepointer (the frame pointer for the calling procedure that was saved by the ENTERinstruction) is then popped from the stack into the EBP register, restoring the callingprocedure’s stack frame.A RET instruction is commonly executed following a LEAVE instruction to returnprogram control to the calling procedure.See “Procedure Calls for Block-Structured Languages” in Chapter 7 of the Intel® 64and IA-32 Architectures Software Developer’s Manual, Volume 1, for detailed information on the use of the ENTER and LEAVE instructions.In 64-bit mode, the instruction’s default operation size is 64 bits; 32-bit operationcannot be encoded. See the summary chart at the beginning of this section forencoding data and limits.OperationIF StackAddressSize = 32THENESP ← EBP;ELSE IF StackAddressSize = 64THEN RSP ← RBP; FI;ELSE IF StackAddressSize = 16THEN SP ← BP; FI;FI;IF OperandSize = 32LEAVE—High Level Procedure ExitVol.
2A 3-603INSTRUCTION SET REFERENCE, A-MTHEN EBP ← Pop();ELSE IF OperandSize = 64THEN RBP ← Pop(); FI;ELSE IF OperandSize = 16THEN BP ← Pop(); FI;FI;Flags AffectedNone.Protected Mode Exceptions#SS(0)If the EBP register points to a location that is not within thelimits of the current stack segment.#PF(fault-code)If a page fault occurs.#AC(0)If alignment checking is enabled and an unaligned memoryreference is made while the current privilege level is 3.#UDIf the LOCK prefix is used.Real-Address Mode Exceptions#GPIf the EBP register points to a location outside of the effectiveaddress space from 0 to FFFFH.#UDIf the LOCK prefix is used.Virtual-8086 Mode Exceptions#GP(0)If the EBP register points to a location outside of the effectiveaddress space from 0 to FFFFH.#PF(fault-code)If a page fault occurs.#AC(0)If alignment checking is enabled and an unaligned memoryreference is made.#UDIf the LOCK prefix is used.Compatibility Mode ExceptionsSame exceptions as in protected mode.64-Bit Mode Exceptions#SS(0)If the stack address is in a non-canonical form.#AC(0)If alignment checking is enabled and an unaligned memoryreference is made while the current privilege level is 3.#UDIf the LOCK prefix is used.3-604 Vol.
2ALEAVE—High Level Procedure ExitINSTRUCTION SET REFERENCE, A-MLFENCE—Load FenceOpcodeInstructionOp/En64-BitModeCompat/ DescriptionLeg Mode0F AE /5LFENCEAValidValidSerializes load operations.Instruction Operand EncodingOp/EnOperand 1Operand 2Operand 3Operand 4ANANANANADescriptionPerforms a serializing operation on all load-from-memory instructions that wereissued prior the LFENCE instruction.
Specifically, LFENCE does not execute until allprior instructions have completed locally, and no later instruction begins executionuntil LFENCE completes. In particular, an instruction that loads from memory andthat precedes an LFENCE receives data from memory prior to completion of theLFENCE. (An LFENCE that follows an instruction that stores to memory mightcomplete before the data being stored have become globally visible.) Instructionsfollowing an LFENCE may be fetched from memory before the LFENCE, but they willnot execute until the LFENCE completes.Weakly ordered memory types can be used to achieve higher processor performancethrough such techniques as out-of-order issue and speculative reads.
The degree towhich a consumer of data recognizes or knows that the data is weakly ordered variesamong applications and may be unknown to the producer of this data. The LFENCEinstruction provides a performance-efficient way of ensuring load ordering betweenroutines that produce weakly-ordered results and routines that consume that data.Processors are free to fetch and cache data speculatively from regions of systemmemory that use the WB, WC, and WT memory types. This speculative fetching canoccur at any time and is not tied to instruction execution.
Thus, it is not ordered withrespect to executions of the LFENCE instruction; data can be brought into the cachesspeculatively just before, during, or after the execution of an LFENCE instruction.This instruction’s operation is the same in non-64-bit modes and 64-bit mode.OperationWait_On_Following_Instructions_Until(preceding_instructions_complete);Intel C/C++ Compiler Intrinsic Equivalentvoid _mm_lfence(void)Exceptions (All Modes of Operation)#UDLFENCE—Load FenceIf the LOCK prefix is used.Vol. 2A 3-605INSTRUCTION SET REFERENCE, A-MLGDT/LIDT—Load Global/Interrupt Descriptor Table RegisterOpcodeInstructionOp/En64-BitModeCompat/ DescriptionLeg Mode0F 01 /2LGDT m16&32AN.E.ValidLoad m into GDTR.0F 01 /3LIDT m16&32AN.E.ValidLoad m into IDTR.0F 01 /2LGDT m16&64AValidN.E.Load m into GDTR.0F 01 /3LIDT m16&64AValidN.E.Load m into IDTR.Instruction Operand EncodingOp/EnOperand 1Operand 2Operand 3Operand 4AModRM:r/m (r)NANANADescriptionLoads the values in the source operand into the global descriptor table register(GDTR) or the interrupt descriptor table register (IDTR).
The source operand specifies a 6-byte memory location that contains the base address (a linear address) andthe limit (size of table in bytes) of the global descriptor table (GDT) or the interruptdescriptor table (IDT). If operand-size attribute is 32 bits, a 16-bit limit (lower 2bytes of the 6-byte data operand) and a 32-bit base address (upper 4 bytes of thedata operand) are loaded into the register. If the operand-size attribute is 16 bits,a 16-bit limit (lower 2 bytes) and a 24-bit base address (third, fourth, and fifth byte)are loaded. Here, the high-order byte of the operand is not used and the high-orderbyte of the base address in the GDTR or IDTR is filled with zeros.The LGDT and LIDT instructions are used only in operating-system software; they arenot used in application programs.
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