Volume 1 Basic Architecture (794100), страница 53
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These encodings are no longer supported due tochanges made in the final version of IEEE Standard 754 that eliminated these encodings.Specifically, the categories of encodings formerly known as pseudo-NaNs, pseudoinfinities, and un-normal numbers are not supported and should not be used asoperand values. The Intel 387 math coprocessor and later IA-32 processors generatean invalid-operation exception when these encodings are encountered as operands.Beginning with the Intel 387 math coprocessor, the encodings formerly known aspseudo-denormal numbers are not generated by IA-32 processors.
When encountered as operands, however, they are handled correctly; that is, they are treated asdenormals and a denormal exception is generated. Pseudo-denormal numbersshould not be used as operand values. They are supported by current IA-32 processors (as described here) to support legacy code.8-20 Vol. 1PROGRAMMING WITH THE X87 FPUTable 8-3. Unsupported Double Extended-Precision Floating-Point Encodings andPseudo-DenormalsClassPositivePseudo-NaNsBiased ExponentIntegerFraction0.011..11.11..110Quiet11..11.10..000.011..11.11..110Signaling01..11.00..01011..11000..000.011..10.00..01011..11.00..00Pseudo-denormals0.000..00.00..00111..11.00..00Pseudo-denormals1.100..00.00..00111..11.00..001.111..10.00..010Unnormals11..01.00..00Pseudo-infinity111..11000..001.111..11.11..110Signaling01..11.00..011.111..11.11..110Quiet11..11.10..00Positive Floating Pseudo-infinityPointUnnormalsNegativeFloating PointNegativePseudo-NaNs← 15 bits →8.3SignificandSign← 63 bits →X86 FPU INSTRUCTION SETThe floating-point instructions that the x87 FPU supports can be grouped into sixfunctional categories:••••Data transfer instructionsBasic arithmetic instructionsComparison instructionsTranscendental instructionsVol.
1 8-21PROGRAMMING WITH THE X87 FPU••Load constant instructionsx87 FPU control instructionsSee Section 5.2, “x87 FPU Instructions,” for a list of the floating-point instructions bycategory.The following section briefly describes the instructions in each category. Detaileddescriptions of the floating-point instructions are given in the Intel® 64 and IA-32Architectures Software Developer’s Manual, Volumes 3A & 3B.8.3.1Escape (ESC) InstructionsAll of the instructions in the x87 FPU instruction set fall into a class of instructionsknown as escape (ESC) instructions. All of these instructions have a common opcodeformat, where the first byte of the opcode is one of the numbers from D8H throughDFH.8.3.2x87 FPU Instruction OperandsMost floating-point instructions require one or two operands, located on the x87 FPUdata-register stack or in memory.
(None of the floating-point instructions acceptimmediate operands.)When an operand is located in a data register, it is referenced relative to the ST(0)register (the register at the top of the register stack), rather than by a physicalregister number. Often the ST(0) register is an implied operand.Operands in memory can be referenced using the same operand addressing methodsdescribed in Section 3.7, “Operand Addressing.”8.3.3Data Transfer InstructionsThe data transfer instructions (see Table 8-4) perform the following operations:•Load a floating-point, integer, or packed BCD operand from memory into theST(0) register.•Store the value in an ST(0) register to memory in floating-point, integer, orpacked BCD format.•Move values between registers in the x87 FPU register stack.The FLD (load floating point) instruction pushes a floating-point operand frommemory onto the top of the x87 FPU data-register stack.
If the operand is in singleprecision or double-precision floating-point format, it is automatically converted todouble extended-precision floating-point format. This instruction can also be used topush the value in a selected x87 FPU data register onto the top of the register stack.8-22 Vol. 1PROGRAMMING WITH THE X87 FPUThe FILD (load integer) instruction converts an integer operand in memory intodouble extended-precision floating-point format and pushes the value onto the top ofthe register stack. The FBLD (load packed decimal) instruction performs the sameload operation for a packed BCD operand in memory.Table 8-4. Data Transfer InstructionsFloating PointIntegerPacked DecimalFLDLoad FloatingPointFILDLoad IntegerFSTStore FloatingPointFISTStore IntegerFSTPStore FloatingPoint and PopFISTPStore Integerand PopFXCHExchange RegisterContentsFCMOVccConditional MoveFBLDLoad PackedDecimalFBSTPStore PackedDecimal and PopThe FST (store floating point) and FIST (store integer) instructions store the value inregister ST(0) in memory in the destination format (floating point or integer, respectively).
Again, the format conversion is carried out automatically.The FSTP (store floating point and pop), FISTP (store integer and pop), and FBSTP(store packed decimal and pop) instructions store the value in the ST(0) registersinto memory in the destination format (floating point, integer, or packed BCD), thenperforms a pop operation on the register stack. A pop operation causes the ST(0)register to be marked empty and the stack pointer (TOP) in the x87 FPU control workto be incremented by 1. The FSTP instruction can also be used to copy the value inthe ST(0) register to another x87 FPU register [ST(i)].The FXCH (exchange register contents) instruction exchanges the value in a selectedregister in the stack [ST(i)] with the value in ST(0).The FCMOVcc (conditional move) instructions move the value in a selected register inthe stack [ST(i)] to register ST(0) if a condition specified with a condition code (cc) issatisfied (see Table 8-5).
The condition being tested for is represented by the statusflags in the EFLAGS register. The condition code mnemonics are appended to theletters “FCMOV” to form the mnemonic for a FCMOVcc instruction.Table 8-5. Floating-Point Conditional Move InstructionsInstruction MnemonicStatus Flag StatesCondition DescriptionFCMOVBCF=1BelowFCMOVNBCF=0Not belowFCMOVEZF=1EqualFCMOVNEZF=0Not equalVol. 1 8-23PROGRAMMING WITH THE X87 FPUTable 8-5. Floating-Point Conditional Move Instructions (Contd.)Instruction MnemonicStatus Flag StatesCondition DescriptionFCMOVBECF=1 or ZF=1Below or equalFCMOVNBECF=0 or ZF=0Not below nor equalFCMOVUPF=1UnorderedFCMOVNUPF=0Not unorderedLike the CMOVcc instructions, the FCMOVcc instructions are useful for optimizingsmall IF constructions.
They also help eliminate branching overhead for IF operationsand the possibility of branch mispredictions by the processor.Software can check if the FCMOVcc instructions are supported by checking theprocessor’s feature information with the CPUID instruction.8.3.4Load Constant InstructionsThe following instructions push commonly used constants onto the top [ST(0)] of thex87 FPU register stack:FLDZLoad +0.0FLD1Load +1.0FLDPILoad πFLDL2TLoad log2 10FLDL2ELoad log2eFLDLG2Load log102FLDLN2Load loge2The constant values have full double extended-precision floating-point precision(64 bits) and are accurate to approximately 19 decimal digits. They are storedinternally in a format more precise than double extended-precision floating point.When loading the constant, the x87 FPU rounds the more precise internal constantaccording to the RC (rounding control) field of the x87 FPU control word.
Theinexact-result exception (#P) is not generated as a result of this rounding, nor isthe C1 flag set in the x87 FPU status word if the value is rounded up. See Section8.3.8, “Pi,” for information on the π constant.8.3.5Basic Arithmetic InstructionsThe following floating-point instructions perform basic arithmetic operations onfloating-point numbers. Where applicable, these instructions match IEEE Standard754:FADD/FADDP8-24 Vol. 1Add floating pointPROGRAMMING WITH THE X87 FPUFIADDFSUB/FSUBPFISUBFSUBR/FSUBRPFISUBRFMUL/FMULPFIMULFDIV/FDIVPFIDIVFDIVR/FDIVRPFIDIVRFABSFCHSFSQRTFPREMFPREM1FRNDINTFXTRACTAdd integer to floating pointSubtract floating pointSubtract integer from floating pointReverse subtract floating pointReverse subtract floating point from integerMultiply floating pointMultiply integer by floating pointDivide floating pointDivide floating point by integerReverse divideReverse divide integer by floating pointAbsolute valueChange signSquare rootPartial remainderIEEE partial remainderRound to integral valueExtract exponent and significandThe add, subtract, multiply and divide instructions operate on the following types ofoperands:••Two x87 FPU data registersAn x87 FPU data register and a floating-point or integer value in memorySee Section 8.1.2, “x87 FPU Data Registers,” for a description of how operands arereferenced on the data register stack.Operands in memory can be in single-precision floating-point, double-precisionfloating-point, word-integer, or doubleword-integer format.
They are converted todouble extended-precision floating-point format automatically.Reverse versions of the subtract (FSUBR) and divide (FDIVR) instructions enable efficient coding. For example, the following options are available with the FSUB andFSUBR instructions for operating on values in a specified x87 FPU data register ST(i)and the ST(0) register:FSUB:ST(0) ← ST(0) − ST(i)ST(i) ← ST(i) − ST(0)FSUBR:ST(0) ← ST(i) − ST(0)ST(i) ← ST(0) − ST(i)These instructions eliminate the need to exchange values between the ST(0) registerand another x87 FPU register to perform a subtraction or division.Vol. 1 8-25PROGRAMMING WITH THE X87 FPUThe pop versions of the add, subtract, multiply, and divide instructions offer theoption of popping the x87 FPU register stack following the arithmetic operation.These instructions operate on values in the ST(i) and ST(0) registers, store the resultin the ST(i) register, and pop the ST(0) register.The FPREM instruction computes the remainder from the division of two operands inthe manner used by the Intel 8087 and Intel 287 math coprocessors; the FPREM1instruction computes the remainder in the manner specified in IEEE Standard 754.The FSQRT instruction computes the square root of the source operand.The FRNDINT instruction returns a floating-point value that is the integral valueclosest to the source value in the direction of the rounding mode specified in the RCfield of the x87 FPU control word.The FABS, FCHS, and FXTRACT instructions perform convenient arithmetic operations.
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