Volume 1 Basic Architecture (794100), страница 52
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Figure 8-8 shows the encoding of these twobytes. Since the upper 5 bits of the first opcode byte are the same for all floatingpoint opcodes (11011B), only the lower 3 bits of this byte are stored in the opcoderegister.8.1.9.1Fopcode Compatibility Sub-modeBeginning with the Pentium 4 and Intel Xeon processors, the IA-32 architectureprovides program control over the storing of the last instruction opcode (sometimesreferred to as the fopcode).
Here, bit 2 of the IA32_MISC_ENABLE MSR enables (set)or disables (clear) the fopcode compatibility mode.If FOP code compatibility mode is enabled, the FOP is defined as it has always beenin previous IA32 implementations (always defined as the FOP of the last non-transparent FP instruction executed before a FSAVE/FSTENV/FXSAVE). If FOP codecompatibility mode is disabled (default), FOP is only valid if the last non-transparentFP instruction executed before a FSAVE/FSTENV/FXSAVE had an unmasked exception.8-14 Vol.
1PROGRAMMING WITH THE X87 FPU71st Instruction Byte2102nd Instruction Byte0708 70x87 FPU Opcode RegisterFigure 8-8. Contents of x87 FPU Opcode RegistersThe fopcode compatibility mode should be enabled only when x87 FPU floating-pointexception handlers are designed to use the fopcode to analyze program performanceor restart a program after an exception has been handled.8.1.10Saving the x87 FPU’s State with FSTENV/FNSTENV andFSAVE/FNSAVEThe FSTENV/FNSTENV and FSAVE/FNSAVE instructions store x87 FPU state information in memory for use by exception handlers and other system and application software.
The FSTENV/FNSTENV instruction saves the contents of the status, control,tag, x87 FPU instruction pointer, x87 FPU operand pointer, and opcode registers. TheFSAVE/FNSAVE instruction stores that information plus the contents of the x87 FPUdata registers. Note that the FSAVE/FNSAVE instruction also initializes the x87 FPU todefault values (just as the FINIT/FNINIT instruction does) after it has saved the original state of the x87 FPU.The manner in which this information is stored in memory depends on the operatingmode of the processor (protected mode or real-address mode) and on the operandsize attribute in effect (32-bit or 16-bit).
See Figures 8-9 through 8-12. In virtual8086 mode or SMM, the real-address mode formats shown in Figure 8-12 is used.See Chapter 24, “System Management,” of the Intel® 64 and IA-32 ArchitecturesSoftware Developer’s Manual, Volume 3B, for information on using the x87 FPU whilein SMM.The FLDENV and FRSTOR instructions allow x87 FPU state information to be loadedfrom memory into the x87 FPU. Here, the FLDENV instruction loads only the status,control, tag, x87 FPU instruction pointer, x87 FPU operand pointer, and opcode registers, and the FRSTOR instruction loads all the x87 FPU registers, including the x87FPU stack registers.Vol.
1 8-15PROGRAMMING WITH THE X87 FPU3132-Bit Protected Mode Format16 150Control Word0Status Word4Tag Word8FPU Instruction Pointer Offset00000Opcode 10...0012FPU Instruction Pointer Selector1620FPU Operand Pointer Offset24FPU Operand Pointer SelectorFor instructions that also store x87 FPU data registers, the eight80-bit registers (R0-R7) follow the above structure in sequence.Figure 8-9.
Protected Mode x87 FPU State Image in Memory, 32-Bit Format31000032-Bit Real-Address Mode Format16 150Control Word0Status Word4Tag Word8FPU Instruction Pointer 15...0012FPU Instruction Pointer 31...160Opcode 10...00FPU Operand Pointer 15...000000FPU Operand Pointer 31...16000000000000162024For instructions that also store x87 FPU data registers, the eight80-bit registers (R0-R7) follow the above structure in sequence.Figure 8-10. Real Mode x87 FPU State Image in Memory, 32-Bit Format8-16 Vol.
1PROGRAMMING WITH THE X87 FPU16-Bit Protected Mode Format015Control Word0Status Word2Tag Word4FPU Instruction Pointer Offset6FPU Instruction Pointer Selector 8FPU Operand Pointer Offset10FPU Operand Pointer Selector12Figure 8-11. Protected Mode x87 FPU State Image in Memory, 16-Bit Format16-Bit Real-Address Mode andVirtual-8086 Mode Format015Control Word0Status Word2Tag WordFPU Instruction Pointer 15...00IP 19..16 0Opcode 10...00FPU Operand Pointer 15...0046810OP 19..16 0 0 0 0 0 0 0 0 0 0 0 0 12Figure 8-12.
Real Mode x87 FPU State Image in Memory, 16-Bit Format8.1.11Saving the x87 FPU’s State with FXSAVEThe FXSAVE and FXRSTOR instructions save and restore, respectively, the x87 FPUstate along with the state of the XMM registers and the MXCSR register. Using theFXSAVE instruction to save the x87 FPU state has two benefits: (1) FXSAVE executesfaster than FSAVE, and (2) FXSAVE saves the entire x87 FPU, MMX, and XMM state inone operation. See Section 10.5, “FXSAVE and FXRSTOR Instructions,” for additionalinformation about these instructions.8.2X87 FPU DATA TYPESThe x87 FPU recognizes and operates on the following seven data types (see Figures8-13): single-precision floating point, double-precision floating point, doubleVol. 1 8-17PROGRAMMING WITH THE X87 FPUextended-precision floating point, signed word integer, signed doubleword integer,signed quadword integer, and packed BCD decimal integers.For detailed information about these data types, see Section 4.2.2, “Floating-PointData Types,” Section 4.2.1.2, “Signed Integers,” and Section 4.7, “BCD and PackedBCD Integers.”With the exception of the 80-bit double extended-precision floating-point format, allof these data types exist in memory only.
When they are loaded into x87 FPU dataregisters, they are converted into double extended-precision floating-point formatand operated on in that format.Denormal values are also supported in each of the floating-point types, as requiredby IEEE Standard 754. When a denormal number in single-precision or double-precision floating-point format is used as a source operand and the denormal exception ismasked, the x87 FPU automatically normalizes the number when it is converted todouble extended-precision format.When stored in memory, the least significant byte of an x87 FPU data-type value isstored at the initial address specified for the value.
Successive bytes from the valueare then stored in successively higher addresses in memory. The floating-pointinstructions load and store memory operands using only the initial address of theoperand.8-18 Vol. 1PROGRAMMING WITH THE X87 FPUSingle-Precision Floating-PointSignExp.23 223130Fraction0Implied IntegerDouble-Precision Floating-PointSignExponent63 6252 51Fraction0Implied IntegerSignDouble Extended-Precision Floating-PointExponent6463 6279 78Fraction0IntegerWord IntegerSign15 140Doubleword IntegerSign31 300Quadword IntegerSignSign63 620Packed BCD IntegersX79 78D17 D16 D15 D14 D13 D12 D11 D1072 71D9D8D7D6D54 Bits = 1 BCD DigitD4D3D2D1D00Figure 8-13. x87 FPU Data Type FormatsAs a general rule, values should be stored in memory in double-precision format. Thisformat provides sufficient range and precision to return correct results with aminimum of programmer attention.
The single-precision format is useful for debugging algorithms, because rounding problems will manifest themselves more quicklyin this format. The double extended-precision format is normally reserved for holdingintermediate results in the x87 FPU registers and constants. Its extra length isdesigned to shield final results from the effects of rounding and overflow/underflowin intermediate calculations. However, when an application requires the maximumrange and precision of the x87 FPU (for data storage, computations, and results),values can be stored in memory in double extended-precision format.8.2.1IndefinitesFor each x87 FPU data type, one unique encoding is reserved for representing thespecial value indefinite.
The x87 FPU produces indefinite values as responses tosome masked floating-point invalid-operation exceptions. See Tables 4-1, 4-3, andVol. 1 8-19PROGRAMMING WITH THE X87 FPU4-4 for the encoding of the integer indefinite, QNaN floating-point indefinite, andpacked BCD integer indefinite, respectively.The binary integer encoding 100..00B represents either of two things, depending onthe circumstances of its use:••The largest negative number supported by the format (–215, –231, or –263)The integer indefinite valueIf this encoding is used as a source operand (as in an integer load or integer arithmetic instruction), the x87 FPU interprets it as the largest negative number representable in the format being used. If the x87 FPU detects an invalid operation whenstoring an integer value in memory with an FIST/FISTP instruction and the invalidoperation exception is masked, the x87 FPU stores the integer indefinite encoding inthe destination operand as a masked response to the exception.
In situations wherethe origin of a value with this encoding may be ambiguous, the invalid-operationexception flag can be examined to see if the value was produced as a response to anexception.8.2.2Unsupported Double Extended-PrecisionFloating-Point Encodings and Pseudo-DenormalsThe double extended-precision floating-point format permits many encodings that donot fall into any of the categories shown in Table 4-3. Table 8-3 shows these unsupported encodings. Some of these encodings were supported by the Intel 287 mathcoprocessor; however, most of them are not supported by the Intel 387 math coprocessor and later IA-32 processors.
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