Volume 1 Basic Architecture (794100), страница 55
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These new algorithms (used in transcendental instructions FSIN, FCOS, FSINCOS, FPTAN, FPATAN, F2XM1, FYL2X, andFYL2XP1) allow a higher level of accuracy than was possible in earlier IA-32 processors and x87 math coprocessors. The accuracy of these instructions is measured interms of units in the last place (ulp). For a given argument x, let f(x) and F(x) bethe correct and computed (approximate) function values, respectively. The error inulps is defined to be:( x ) – F ( x )error = f-------------------------k – 632Vol. 1 8-31PROGRAMMING WITH THE X87 FPUwhere k is an integer such that:1≤2–kf ( x ) < 2.With the Pentium processor and later IA-32 processors, the worst case error ontranscendental functions is less than 1 ulp when rounding to the nearest (even) andless than 1.5 ulps when rounding in other modes.
The functions are guaranteed to bemonotonic, with respect to the input operands, throughout the domain supported bythe instruction.The instructions FYL2X and FYL2XP1 are two operand instructions and are guaranteed to be within 1 ulp only when y equals 1. When y is not equal to 1, the maximumulp error is always within 1.35 ulps in round to nearest mode. (For the two operandfunctions, monotonicity was proved by holding one of the operands constant.)8.3.11x87 FPU Control InstructionsThe following instructions control the state and modes of operation of the x87 FPU.They also allow the status of the x87 FPU to be examined:FINIT/FNINIT Initialize x87 FPUFLDCWLoad x87 FPU control wordFSTCW/FNSTCWStore x87 FPU control wordFSTSW/FNSTSWStore x87 FPU status wordFCLEX/FNCLEXClear x87 FPU exception flagsFLDENVLoad x87 FPU environmentFSTENV/FNSTENVStore x87 FPU environmentFRSTORRestore x87 FPU stateFSAVE/FNSAVESave x87 FPU stateFINCSTPIncrement x87 FPU register stack pointerFDECSTPDecrement x87 FPU register stack pointerFFREEFree x87 FPU registerFNOPNo operationWAIT/FWAITCheck for and handle pending unmaskedx87 FPU exceptionsThe FINIT/FNINIT instructions initialize the x87 FPU and its internal registers todefault values.The FLDCW instructions loads the x87 FPU control word register with a value frommemory.
The FSTCW/FNSTCW and FSTSW/FNSTSW instructions store the x87 FPU8-32 Vol. 1PROGRAMMING WITH THE X87 FPUcontrol and status words, respectively, in memory (or for an FSTSW/FNSTSWinstruction in a general-purpose register).The FSTENV/FNSTENV and FSAVE/FNSAVE instructions save the x87 FPU environment and state, respectively, in memory. The x87 FPU environment includes all thex87 FPU’s control and status registers; the x87 FPU state includes the x87 FPU environment and the data registers in the x87 FPU register stack. (The FSAVE/FNSAVEinstruction also initializes the x87 FPU to default values, like the FINIT/FNINITinstruction, after it saves the original state of the x87 FPU.)The FLDENV and FRSTOR instructions load the x87 FPU environment and state,respectively, from memory into the x87 FPU. These instructions are commonly usedwhen switching tasks or contexts.The WAIT/FWAIT instructions are synchronization instructions.
(They are actuallymnemonics for the same opcode.) These instructions check the x87 FPU status wordfor pending unmasked x87 FPU exceptions. If any pending unmasked x87 FPU exceptions are found, they are handled before the processor resumes execution of theinstructions (integer, floating-point, or system instruction) in the instruction stream.The WAIT/FWAIT instructions are provided to allow synchronization of instructionexecution between the x87 FPU and the processor’s integer unit. See Section 8.6,“x87 FPU Exception Synchronization,” for more information on the use of theWAIT/FWAIT instructions.8.3.12Waiting vs.
Non-waiting InstructionsAll of the x87 FPU instructions except a few special control instructions perform a waitoperation (similar to the WAIT/FWAIT instructions), to check for and handle pendingunmasked x87 FPU floating-point exceptions, before they perform their primaryoperation (such as adding two floating-point numbers). These instructions are calledwaiting instructions. Some of the x87 FPU control instructions, such asFSTSW/FNSTSW, have both a waiting and a non-waiting version.
The waiting version(with the “F” prefix) executes a wait operation before it performs its primary operation; whereas, the non-waiting version (with the “FN” prefix) ignores pendingunmasked exceptions.Non-waiting instructions allow software to save the current x87 FPU state withoutfirst handling pending exceptions or to reset or reinitialize the x87 FPU withoutregard for pending exceptions.NOTESWhen operating a Pentium or Intel486 processor in MS-DOS compatibility mode, it is possible (under unusual circumstances) for a nonwaiting instruction to be interrupted prior to being executed tohandle a pending x87 FPU exception. The circumstances where thiscan happen and the resulting action of the processor are described inVol. 1 8-33PROGRAMMING WITH THE X87 FPUSection D.2.1.3, “No-Wait x87 FPU Instructions Can Get x87 FPUInterrupt in Window.”When operating a P6 family, Pentium 4, or Intel Xeon processor inMS-DOS compatibility mode, non-waiting instructions can not beinterrupted in this way (see Section D.2.2, “MS-DOS CompatibilitySub-mode in the P6 Family and Pentium 4 Processors”).8.3.13Unsupported x87 FPU InstructionsThe Intel 8087 instructions FENI and FDISI and the Intel 287 math coprocessorinstruction FSETPM perform no function in the Intel 387 math coprocessor and laterIA-32 processors.
If these opcodes are detected in the instruction stream, the x87FPU performs no specific operation and no internal x87 FPU states are affected.8.4X87 FPU FLOATING-POINT EXCEPTION HANDLINGThe x87 FPU detects the six classes of exception conditions described in Section 4.9,“Overview of Floating-Point Exceptions”:•Invalid operation (#I), with two subclasses:— Stack overflow or underflow (#IS)— Invalid arithmetic operation (#IA)•••••Denormalized operand (#D)Divide-by-zero (#Z)Numeric overflow (#O)Numeric underflow (#U)Inexact result (precision) (#P)Each of the six exception classes has a corresponding flag bit in the x87 FPU statusword and a mask bit in the x87 FPU control word (see Section 8.1.3, “x87 FPU StatusRegister,” and Section 8.1.5, “x87 FPU Control Word,” respectively).
In addition, theexception summary (ES) flag in the status word indicates when one or moreunmasked exceptions has been detected. The stack fault (SF) flag (also in the statusword) distinguishes between the two types of invalid-operation exceptions.The mask bits can be set with FLDCW, FRSTOR, or FXRSTOR; they can be read witheither FSTCW/FNSTCW, FSAVE/FNSAVE, or FXSAVE. The flag bits can be read withthe FSTSW/FNSTSW, FSAVE/FNSAVE, or FXSAVE instruction.NOTESection 4.9.1, “Floating-Point Exception Conditions,” provides ageneral overview of how the IA-32 processor detects and handles the8-34 Vol. 1PROGRAMMING WITH THE X87 FPUvarious classes of floating-point exceptions.
This information pertainsto x87 FPU as well as SSE/SSE2/SSE3 extensions.The following sections give specific information about how the x87 FPU handlesfloating-point exceptions that are unique to the x87 FPU.8.4.1Arithmetic vs. Non-arithmetic InstructionsWhen dealing with floating-point exceptions, it is useful to distinguish betweenarithmetic instructions and non-arithmetic instructions. Non-arithmeticinstructions have no operands or do not make substantial changes to their operands.Arithmetic instructions do make significant changes to their operands; in particular,they make changes that could result in floating-point exceptions being signaled.Table 8-9 lists the non-arithmetic and arithmetic instructions.
It should be noted thatsome non-arithmetic instructions can signal a floating-point stack (fault) exception,but this exception is not the result of an operation on an operand.Table 8-9. Arithmetic and Non-arithmetic InstructionsNon-arithmetic InstructionsArithmetic InstructionsFABSF2XM1FCHSFADD/FADDPFCLEXFBLDFDECSTPFBSTPFFREEFCOM/FCOMP/FCOMPPFINCSTPFCOSFINIT/FNINITFDIV/FDIVP/FDIVR/FDIVRPFLD (register-to-register)FIADDFLD (extended format from memory)FICOM/FICOMPFLD constantFIDIV/FIDIVRFLDCWFILDFLDENVFIMULFNOPFIST/FISTP1FRSTORFISUB/FISUBRFSAVE/FNSAVEFLD (single and double)FST/FSTP (register-to-register)FMUL/FMULPFSTP (extended format to memory)FPATANFSTCW/FNSTCWFPREM/FPREM1FSTENV/FNSTENVFPTANVol.
1 8-35PROGRAMMING WITH THE X87 FPUTable 8-9. Arithmetic and Non-arithmetic Instructions (Contd.)Non-arithmetic InstructionsArithmetic InstructionsFSTSW/FNSTSWFRNDINTWAIT/FWAITFSCALEFXAMFSINFXCHFSINCOSFSQRTFST/FSTP (single and double)FSUB/FSUBP/FSUBR/FSUBRPFTSTFUCOM/FUCOMP/FUCOMPPFXTRACTFYL2X/FYL2XP1NOTE:1. The FISTTP instruction in SSE3 is an arithmetic x87 FPU instruction.8.5X87 FPU FLOATING-POINT EXCEPTION CONDITIONSThe following sections describe the various conditions that cause a floating-pointexception to be generated by the x87 FPU and the masked response of the x87 FPUwhen these conditions are detected. Intel® 64 and IA-32 Architectures SoftwareDeveloper’s Manual, Volumes 2A & 2B, list the floating-point exceptions that can besignaled for each floating-point instruction.See Section 4.9.2, “Floating-Point Exception Priority,” for a description of the rules forexception precedence when more than one floating-point exception condition isdetected for an instruction.8.5.1Invalid Operation ExceptionThe floating-point invalid-operation exception occurs in response to two sub-classesof operations:••Stack overflow or underflow (#IS)Invalid arithmetic operand (#IA)The flag for this exception (IE) is bit 0 of the x87 FPU status word, and the mask bit(IM) is bit 0 of the x87 FPU control word.
The stack fault flag (SF) of the x87 FPUstatus word indicates the type of operation that caused the exception. When the SFflag is set to 1, a stack operation has resulted in stack overflow or underflow; when8-36 Vol. 1PROGRAMMING WITH THE X87 FPUthe flag is cleared to 0, an arithmetic instruction has encountered an invalid operand.Note that the x87 FPU explicitly sets the SF flag when it detects a stack overflow orunderflow condition, but it does not explicitly clear the flag when it detects an invalidarithmetic-operand condition. As a result, the state of the SF flag can be 1 followingan invalid-arithmetic-operation exception, if it was not cleared from the last time astack overflow or underflow condition occurred. See Section 8.1.3.4, “Stack FaultFlag,” for more information about the SF flag.8.5.1.1Stack Overflow or Underflow Exception (#IS)The x87 FPU tag word keeps track of the contents of the registers in the x87 FPUregister stack (see Section 8.1.7, “x87 FPU Tag Word”).
It then uses this informationto detect two different types of stack faults:•Stack overflow — An instruction attempts to load a non-empty x87 FPU registerfrom memory. A non-empty register is defined as a register containing a zero(tag value of 01), a valid value (tag value of 00), or a special value (tag value of10).•Stack underflow — An instruction references an empty x87 FPU register as asource operand, including attempting to write the contents of an empty registerto memory.
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