Volume 1 Basic Architecture (794100), страница 57
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The top-of-stack pointer (TOP) and source and destination operandsremain unchanged. Because the data in the stack is in double extended-precisionformat, the exception handler has the option either of re-executing the storeinstruction after proper adjustment of the operand or of rounding the significandon the stack to the destination's precision as the standard requires. Theexception handler should ultimately store a value into the destination location inmemory if the program is to continue.•Destination is the register stack — The significand of the result is roundedaccording to current settings of the precision and rounding control bits in the x87FPU control word and the exponent of the result is adjusted by dividing it by224576. (For instructions not affected by the precision field, the significand isrounded to double-extended precision.) The resulting value is stored in thedestination operand. Condition code bit C1 in the x87 FPU status word (called inthis situation the “round-up bit”) is set if the significand was rounded upward andcleared if the result was rounded toward 0.
After the result is stored, the OE flagis set and a software exception handler is invoked. The scaling bias value 24,576is equal to 3 ∗ 213. Biasing the exponent by 24,576 normally translates thenumber as nearly as possible to the middle of the double extended-precisionfloating-point exponent range so that, if desired, it can be used in subsequentscaled operations with less risk of causing further exceptions.When using the FSCALE instruction, massive overflow can occur, where the resultis too large to be represented, even with a bias-adjusted exponent. Here, ifoverflow occurs again, after the result has been biased, a properly signed ∞ isstored in the destination operand.8.5.5Numeric Underflow Exception (#U)The x87 FPU detects a floating-point numeric underflow condition whenever therounded result of an arithmetic instruction is tiny; that is, less than the smallestpossible normalized, finite value that will fit into the floating-point format of thedestination operand.
(See Section 4.9.1.5, “Numeric Underflow Exception (#U),” foradditional information about the numeric underflow exception.)Like numeric overflow, numeric underflow can occur on arithmetic operations wherethe result is stored in an x87 FPU data register. It can also occur on store floatingpoint operations (with the FST and FSTP instructions), where a within-range value ina data register is stored in memory in the smaller single-precision or double-precision floating-point formats. A numeric underflow exception cannot occur whenstoring values in an integer or BCD integer format, because a tiny value is alwaysrounded to an integral value of 0 or 1, depending on the rounding mode in effect.Vol. 1 8-41PROGRAMMING WITH THE X87 FPUThe flag (UE) for the numeric-underflow exception is bit 4 of the x87 FPU statusword, and the mask bit (UM) is bit 4 of the x87 FPU control word.When a numeric-underflow condition occurs and the exception is masked, the x87FPU performs the operation described in Section 4.9.1.5, “Numeric Underflow Exception (#U).”When the exception is not masked, the action of the x87 FPU depends on whether theinstruction is supposed to store the result in a memory location or on the x87 FPUresister stack.•Destination is a memory location — (Can occur only with a store instruction.)The UE flag is set and a software exception handler is invoked (see Section 8.7,“Handling x87 FPU Exceptions in Software”).
The top-of-stack pointer (TOP) andsource and destination operands remain unchanged, and no result is stored inmemory.Because the data in the stack is in double extended-precision format, theexception handler has the option either of re-exchanges the store instructionafter proper adjustment of the operand or of rounding the significand on thestack to the destination's precision as the standard requires. The exceptionhandler should ultimately store a value into the destination location in memory ifthe program is to continue.•Destination is the register stack — The significand of the result is roundedaccording to current settings of the precision and rounding control bits in the x87FPU control word and the exponent of the result is adjusted by multiplying it by224576. (For instructions not affected by the precision field, the significand isrounded to double extended precision.) The resulting value is stored in thedestination operand. Condition code bit C1 in the x87 FPU status register (actinghere as a “round-up bit”) is set if the significand was rounded upward and clearedif the result was rounded toward 0.
After the result is stored, the UE flag is setand a software exception handler is invoked. The scaling bias value 24,576 is thesame as is used for the overflow exception and has the same effect, which is totranslate the result as nearly as possible to the middle of the double extendedprecision floating-point exponent range.When using the FSCALE instruction, massive underflow can occur, where theresult is too tiny to be represented, even with a bias-adjusted exponent. Here, ifunderflow occurs again after the result has been biased, a properly signed 0 isstored in the destination operand.8.5.6Inexact-Result (Precision) Exception (#P)The inexact-result exception (also called the precision exception) occurs if the resultof an operation is not exactly representable in the destination format.
(See Section4.9.1.6, “Inexact-Result (Precision) Exception (#P),” for additional information aboutthe numeric overflow exception.) Note that the transcendental instructions (FSIN,FCOS, FSINCOS, FPTAN, FPATAN, F2XM1, FYL2X, and FYL2XP1) by nature produceinexact results.8-42 Vol. 1PROGRAMMING WITH THE X87 FPUThe inexact-result exception flag (PE) is bit 5 of the x87 FPU status word, and themask bit (PM) is bit 5 of the x87 FPU control word.If the inexact-result exception is masked when an inexact-result condition occurs anda numeric overflow or underflow condition has not occurred, the x87 FPU handles theexception as describe in Section 4.9.1.6, “Inexact-Result (Precision) Exception (#P),”with one additional action.
The C1 (round-up) bit in the x87 FPU status word is set toindicate whether the inexact result was rounded up (C1 is set) or “not rounded up”(C1 is cleared). In the “not rounded up” case, the least-significant bits of the inexactresult are truncated so that the result fits in the destination format.If the inexact-result exception is not masked when an inexact result occurs andnumeric overflow or underflow has not occurred, the x87 FPU handles the exceptionas described in the previous paragraph and, in addition, invokes a software exceptionhandler.If an inexact result occurs in conjunction with numeric overflow or underflow, the x87FPU carries out one of the following operations:•If an inexact result occurs in conjunction with masked overflow or underflow, theOE or UE flag and the PE flag are set and the result is stored as described for theoverflow or underflow exceptions (see Section 8.5.4, “Numeric OverflowException (#O),” or Section 8.5.5, “Numeric Underflow Exception (#U)”).
If theinexact result exception is unmasked, the x87 FPU also invokes a softwareexception handler.•If an inexact result occurs in conjunction with unmasked overflow or underflowand the destination operand is a register, the OE or UE flag and the PE flag areset, the result is stored as described for the overflow or underflow exceptions(see Section 8.5.4, “Numeric Overflow Exception (#O),” or Section 8.5.5,“Numeric Underflow Exception (#U)”) and a software exception handler isinvoked.If an unmasked numeric overflow or underflow exception occurs and the destinationoperand is a memory location (which can happen only for a floating-point store), theinexact-result condition is not reported and the C1 flag is cleared.8.6X87 FPU EXCEPTION SYNCHRONIZATIONBecause the integer unit and x87 FPU are separate execution units, it is possible forthe processor to execute floating-point, integer, and system instructions concurrently.
No special programming techniques are required to gain the advantages ofconcurrent execution. (Floating-point instructions are placed in the instructionstream along with the integer and system instructions.) However, concurrent execution can cause problems for floating-point exception handlers.This problem is related to the way the x87 FPU signals the existence of unmaskedfloating-point exceptions. (Special exception synchronization is not required formasked floating-point exceptions, because the x87 FPU always returns a maskedresult to the destination operand.)Vol. 1 8-43PROGRAMMING WITH THE X87 FPUWhen a floating-point exception is unmasked and the exception condition occurs, thex87 FPU stops further execution of the floating-point instruction and signals theexception event. On the next occurrence of a floating-point instruction or aWAIT/FWAIT instruction in the instruction stream, the processor checks the ES flag inthe x87 FPU status word for pending floating-point exceptions.
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