Volume 1 Basic Architecture (794100), страница 61
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The EMMS instruction is provided toprevent this problem by marking the x87 FPU tag word as empty.The EMMS instruction should be used in each of the following cases:•When an application using the x87 FPU instructions calls an MMX technologylibrary/DLL (use the EMMS instruction at the end of the MMX code).9-12 Vol. 1PROGRAMMING WITH INTEL® MMX™ TECHNOLOGY•When an application using MMX instructions calls a x87 FPU floating-pointlibrary/DLL (use the EMMS instruction before calling the x87 FPU code).•When a switch is made between MMX code in a task or thread and other tasks orthreads in cooperative operating systems, unless it is certain that more MMXinstructions will be executed before any x87 FPU code.EMMS is not required when mixing MMX technology instructions withSSE/SSE2/SSE3 instructions (see Section 11.6.7, “Interaction of SSE/SSE2 Instructions with x87 FPU and MMX Instructions”).9.6.4Mixing MMX and x87 FPU InstructionsAn application can contain both x87 FPU floating-point and MMX instructions.However, frequent transitions between MMX and x87 FPU instructions are not recommended, because they can degrade performance in some processor implementations.
When mixing MMX code with x87 FPU code, follow these guidelines:••Keep the code in separate modules, procedures, or routines.•When transitioning between MMX code and x87 FPU code, save the MMX registerstate (if it will be needed in the future) and execute an EMMS instruction to emptythe MMX state.•When transitioning between x87 FPU code and MMX code, save the x87 FPU stateif it will be needed in the future.Do not rely on register contents across transitions between x87 FPU and MMXcode modules.9.6.5Interfacing with MMX CodeMMX technology enables direct access to all the MMX registers. This means that allexisting interface conventions that apply to the use of the processor’s generalpurpose registers (EAX, EBX, etc.) also apply to the use of MMX registers.An efficient interface to MMX routines might pass parameters and return valuesthrough the MMX registers or through a combination of memory locations (via thestack) and MMX registers.
Do not use the EMMS instruction or mix MMX and x87 FPUcode when using to the MMX registers to pass parameters.If a high-level language that does not support the MMX data types directly is used,the MMX data types can be defined as a 64-bit structure containing packed datatypes.When implementing MMX instructions in high-level languages, other approaches canbe taken, such as:•Passing parameters to an MMX routine by passing a pointer to a structure via thestack.•Returning a value from a function by returning a pointer to a structure.Vol. 1 9-13PROGRAMMING WITH INTEL® MMX™ TECHNOLOGY9.6.6Using MMX Code in a Multitasking Operating SystemEnvironmentAn application needs to identify the nature of the multitasking operating system onwhich it runs. Each task retains its own state which must be saved when a task switchoccurs.
The processor state (context) consists of the general-purpose registers andthe floating-point and MMX registers.Operating systems can be classified into two types:••Cooperative multitasking operating systemPreemptive multitasking operating systemCooperative multitasking operating systems do not save the FPU or MMX state whenperforming a context switch. Therefore, the application needs to save the relevantstate before relinquishing direct or indirect control to the operating system.Preemptive multitasking operating systems are responsible for saving and restoringthe FPU and MMX state when performing a context switch.
Therefore, the applicationdoes not have to save or restore the FPU and MMX state.9.6.7Exception Handling in MMX CodeMMX instructions generate the same type of memory-access exceptions as otherIA-32 instructions (page fault, segment not present, and limit violations). Existingexception handlers do not have to be modified to handle these types of exceptions forMMX code.Unless there is a pending floating-point exception, MMX instructions do not generatenumeric exceptions. Therefore, there is no need to modify existing exceptionhandlers or add new ones to handle numeric exceptions.If a floating-point exception is pending, the subsequent MMX instruction generates anumeric error exception (interrupt 16 and/or assertion of the FERR# pin).
The MMXinstruction resumes execution upon return from the exception handler.9.6.8Register MappingMMX registers and their tags are mapped to physical locations of the floating-pointregisters and their tags. Register aliasing and mapping is described in more detail inChapter 11, “Intel® MMX™ Technology System Programming,” in the Intel® 64 andIA-32 Architectures Software Developer’s Manual, Volume 3A.9.6.9Effect of Instruction Prefixes on MMX InstructionsTable 9-3 describes the effect of instruction prefixes on MMX instructions.
Unpredictable behavior can range from being treated as a reserved operation on one genera-9-14 Vol. 1PROGRAMMING WITH INTEL® MMX™ TECHNOLOGYtion of IA-32 processors to generating an invalid opcode exception on anothergeneration of processors.Table 9-3. Effect of Prefixes on MMX InstructionsPrefix TypeEffect on MMX InstructionsAddress Size Prefix (67H)Affects instructions with a memory operand.Reserved for instructions without a memory operand andmay result in unpredictable behavior.Operand Size (66H)Reserved and may result in unpredictable behavior.Segment Override (2EH, 36H,3EH, 26H, 64H, 65H)Affects instructions with a memory operand.Repeat Prefix (F3H)Reserved and may result in unpredictable behavior.Repeat NE Prefix(F2H)Reserved and may result in unpredictable behavior.Lock Prefix (F0H)Reserved; generates invalid opcode exception (#UD).Branch Hint Prefixes (2EH and3EH)Reserved and may result in unpredictable behavior.Reserved for instructions without a memory operand andmay result in unpredictable behavior.See “Instruction Prefixes” in Chapter 2, “Instruction Format,” of the Intel® 64 andIA-32 Architectures Software Developer’s Manual, Volume 2A, for a description of theinstruction prefixes.Vol.
1 9-15PROGRAMMING WITH INTEL® MMX™ TECHNOLOGY9-16 Vol. 1CHAPTER 10PROGRAMMING WITHSTREAMING SIMD EXTENSIONS (SSE)The streaming SIMD extensions (SSE) were introduced into the IA-32 architecture inthe Pentium III processor family. These extensions enhance the performance of IA-32processors for advanced 2-D and 3-D graphics, motion video, image processing,speech recognition, audio synthesis, telephony, and video conferencing.This chapter describes SSE.
Chapter 11, “Programming with Streaming SIMD Extensions 2 (SSE2),” provides information to assist in writing application programs thatuse SSE2 extensions. Chapter 12, “Programming with SSE3 and SupplementalSSE3,” provides this information for SSE3 extensions.10.1OVERVIEW OF SSE EXTENSIONSIntel MMX technology introduced single-instruction multiple-data (SIMD) capabilityinto the IA-32 architecture, with the 64-bit MMX registers, 64-bit packed integer datatypes, and instructions that allowed SIMD operations to be performed on packedintegers. SSE extensions expand the SIMD execution model by adding facilities forhandling packed and scalar single-precision floating-point values contained in128-bit registers.If CPUID.01H:EDX.SSE[bit 25] = 1, SSE extensions are present.SSE extensions add the following features to the IA-32 architecture, while maintaining backward compatibility with all existing IA-32 processors, applications andoperating systems.•Eight 128-bit data registers (called XMM registers) in non-64-bit modes; sixteenXMM registers are available in 64-bit mode.•The 32-bit MXCSR register, which provides control and status bits for operationsperformed on XMM registers.•The 128-bit packed single-precision floating-point data type (four IEEE singleprecision floating-point values packed into a double quadword).•Instructions that perform SIMD operations on single-precision floating-pointvalues and that extend SIMD operations that can be performed on integers:— 128-bit Packed and scalar single-precision floating-point instructions thatoperate on data located in MMX registers— 64-bit SIMD integer instructions that support additional operations on packedinteger operands located in MMX registers•Instructions that save and restore the state of the MXCSR register.Vol.
1 10-1PROGRAMMING WITH STREAMING SIMD EXTENSIONS (SSE)•Instructions that support explicit prefetching of data, control of the cacheabilityof data, and control the ordering of store operations.•Extensions to the CPUID instruction.These features extend the IA-32 architecture’s SIMD programming model in fourimportant ways:•The ability to perform SIMD operations on four packed single-precision floatingpoint values enhances the performance of IA-32 processors for advanced mediaand communications applications that use computation-intensive algorithms toperform repetitive operations on large arrays of simple, native data elements.•The ability to perform SIMD single-precision floating-point operations in XMMregisters and SIMD integer operations in MMX registers provides greaterflexibility and throughput for executing applications that operate on large arraysof floating-point and integer data.•Cache control instructions provide the ability to stream data in and out of XMMregisters without polluting the caches and the ability to prefetch data to selectedcache levels before it is actually used.
Applications that require regular access tolarge amounts of data benefit from these prefetching and streaming storecapabilities.•The SFENCE (store fence) instruction provides greater control over the orderingof store operations when using weakly-ordered memory types.SSE extensions are fully compatible with all software written for IA-32 processors.
Allexisting software continues to run correctly, without modification, on processors thatincorporate SSE extensions. Enhancements to CPUID permit detection of SSE extensions. SSE extensions are accessible from all IA-32 execution modes: protectedmode, real address mode, and virtual-8086 mode.The following sections of this chapter describe the programming environment for SSEextensions, including: XMM registers, the packed single-precision floating-point datatype, and SSE instructions. For additional information, see:••Section 11.6, “Writing Applications with SSE/SSE2 Extensions”.•Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volumes2A & 2B, provide a detailed description of these instructions.•Chapter 12, “System Programming for Streaming SIMD Instruction Sets,” in theIntel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 3A,gives guidelines for integrating these extensions into an operating-systemenvironment.Section 11.5, “SSE, SSE2, and SSE3 Exceptions,” describes the exceptions thatcan be generated with SSE/SSE2/SSE3 instructions.10-2 Vol.
1PROGRAMMING WITH STREAMING SIMD EXTENSIONS (SSE)10.2SSE PROGRAMMING ENVIRONMENTFigure 10-1 shows the execution environment for the SSE extensions. All SSEinstructions operate on the XMM registers, MMX registers, and/or memory asfollows:•XMM registers — These eight registers (see Figure 10-2 and Section 10.2.2,“XMM Registers”) are used to operate on packed or scalar single-precisionfloating-point data. Scalar operations are operations performed on individual(unpacked) single-precision floating-point values stored in the low doubleword ofan XMM register.
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