Volume 1 Basic Architecture (794100), страница 64
Текст из файла (страница 64)
The value ofthe immediate operand allows the selection of any of 8 compare conditions: equal,less than, less than equal, unordered, not equal, not less than, not less than or equal,or ordered.Vol. 1 10-13PROGRAMMING WITH STREAMING SIMD EXTENSIONS (SSE)The CMPSS (compare scalar single-precision, floating-point values) instructioncompares the low values from two packed single-precision floating-point operands,using an immediate operand as a predicate, and returns a 32-bit mask result of all 1sor all 0s for the comparison to the low doubleword of the destination operand.
Theimmediate operand selects the compare conditions as with the CMPPS instruction.The COMISS (compare scalar single-precision floating-point values and set EFLAGS)and UCOMISS (unordered compare scalar single-precision floating-point values andset EFLAGS) instructions compare the low values of two packed single-precisionfloating-point operands and set the ZF, PF, and CF flags in the EFLAGS register toshow the result (greater than, less than, equal, or unordered). These two instructions differ as follows: the COMISS instruction signals a floating-point invalid-operation (#I) exception when a source operand is either a QNaN or an SNaN; theUCOMISS instruction only signals an invalid-operation exception when a sourceoperand is an SNaN.10.4.2.2SSE Shuffle and Unpack InstructionsSSE shuffle and unpack instructions shuffle or interleave the contents of two packedsingle-precision floating-point values and store the results in the destinationoperand.The SHUFPS (shuffle packed single-precision floating-point values) instruction placesany two of the four packed single-precision floating-point values from the destinationoperand into the two low-order doublewords of the destination operand, and placesany two of the four packed single-precision floating-point values from the sourceoperand in the two high-order doublewords of the destination operand (seeFigure 10-7).
By using the same register for the source and destination operands,the SHUFPS instruction can shuffle four single-precision floating-point values intoany order.DESTX3SRCY3DESTY3 ... Y0X2Y2Y3 ... Y0X1Y1X3 ... X0X0Y0X3 ... X0Figure 10-7. SHUFPS Instruction, Packed Shuffle Operation10-14 Vol. 1PROGRAMMING WITH STREAMING SIMD EXTENSIONS (SSE)The UNPCKHPS (unpack and interleave high packed single-precision floating-pointvalues) instruction performs an interleaved unpack of the high-order single-precisionfloating-point values from the source and destination operands and stores the resultin the destination operand (see Figure 10-8).DESTX3X2X1X0SRCY3Y2Y1Y0DESTY3X3Y2X2Figure 10-8.
UNPCKHPS Instruction, High Unpack and Interleave OperationThe UNPCKLPS (unpack and interleave low packed single-precision floating-pointvalues) instruction performs an interleaved unpack of the low-order single-precisionfloating-point values from the source and destination operands and stores the resultin the destination operand (see Figure 10-9).DESTX3X2X1SRCY3Y2Y1DESTY1X1Y0X0Y0X0Figure 10-9. UNPCKLPS Instruction, Low Unpack and Interleave Operation10.4.3SSE Conversion InstructionsSSE conversion instructions (see Figure 11-8) support packed and scalar conversionsbetween single-precision floating-point and doubleword integer formats.Vol. 1 10-15PROGRAMMING WITH STREAMING SIMD EXTENSIONS (SSE)The CVTPI2PS (convert packed doubleword integers to packed single-precisionfloating-point values) instruction converts two packed signed doubleword integersinto two packed single-precision floating-point values. When the conversion isinexact, the result is rounded according to the rounding mode selected in the MXCSRregister.The CVTSI2SS (convert doubleword integer to scalar single-precision floating-pointvalue) instruction converts a signed doubleword integer into a single-precisionfloating-point value.
When the conversion is inexact, the result is rounded accordingto the rounding mode selected in the MXCSR register.The CVTPS2PI (convert packed single-precision floating-point values to packeddoubleword integers) instruction converts two packed single-precision floating-pointvalues into two packed signed doubleword integers. When the conversion is inexact,the result is rounded according to the rounding mode selected in the MXCSR register.The CVTTPS2PI (convert with truncation packed single-precision floating-pointvalues to packed doubleword integers) instruction is similar to the CVTPS2PI instruction, except that truncation is used to round a source value to an integer value (seeSection 4.8.4.2, “Truncation with SSE and SSE2 Conversion Instructions”).The CVTSS2SI (convert scalar single-precision floating-point value to doublewordinteger) instruction converts a single-precision floating-point value into a signeddoubleword integer.
When the conversion is inexact, the result is rounded accordingto the rounding mode selected in the MXCSR register. The CVTTSS2SI (convert withtruncation scalar single-precision floating-point value to doubleword integer) instruction is similar to the CVTSS2SI instruction, except that truncation is used to roundthe source value to an integer value (see Section 4.8.4.2, “Truncation with SSE andSSE2 Conversion Instructions”).10.4.4SSE 64-Bit SIMD Integer InstructionsSSE extensions add the following 64-bit packed integer instructions to the IA-32architecture. These instructions operate on data in MMX registers and 64-bit memorylocations.NOTEWhen SSE2 extensions are present in an IA-32 processor, theseinstructions are extended to operate on 128-bit operands in XMMregisters and 128-bit memory locations.The PAVGB (compute average of packed unsigned byte integers) and PAVGW(compute average of packed unsigned word integers) instructions compute a SIMDaverage of two packed unsigned byte or word integer operands, respectively.
Foreach corresponding pair of data elements in the packed source operands, theelements are added together, a 1 is added to the temporary sum, and that result isshifted right one bit position.10-16 Vol. 1PROGRAMMING WITH STREAMING SIMD EXTENSIONS (SSE)The PEXTRW (extract word) instruction copies a selected word from an MMX registerinto a general-purpose register.The PINSRW (insert word) instruction copies a word from a general-purpose registeror from memory into a selected word location in an MMX register.The PMAXUB (maximum of packed unsigned byte integers) instruction compares thecorresponding unsigned byte integers in two packed operands and returns thegreater of each comparison to the destination operand.The PMINUB (minimum of packed unsigned byte integers) instruction compares thecorresponding unsigned byte integers in two packed operands and returns the lesserof each comparison to the destination operand.The PMAXSW (maximum of packed signed word integers) instruction compares thecorresponding signed word integers in two packed operands and returns the greaterof each comparison to the destination operand.The PMINSW (minimum of packed signed word integers) instruction compares thecorresponding signed word integers in two packed operands and returns the lesser ofeach comparison to the destination operand.The PMOVMSKB (move byte mask) instruction creates an 8-bit mask from the packedbyte integers in an MMX register and stores the result in the low byte of a generalpurpose register.
The mask contains the most significant bit of each byte in the MMXregister. (When operating on 128-bit operands, a 16-bit mask is created.)The PMULHUW (multiply packed unsigned word integers and store high result)instruction performs a SIMD unsigned multiply of the words in the two source operands and returns the high word of each result to an MMX register.The PSADBW (compute sum of absolute differences) instruction computes the SIMDabsolute differences of the corresponding unsigned byte integers in two source operands, sums the differences, and stores the sum in the low word of the destinationoperand.The PSHUFW (shuffle packed word integers) instruction shuffles the words in thesource operand according to the order specified by an 8-bit immediate operand andreturns the result to the destination operand.10.4.5MXCSR State Management InstructionsThe MXCSR state management instructions (LDMXCSR and STMXCSR) load and savethe state of the MXCSR register, respectively.
The LDMXCSR instruction loads theMXCSR register from memory, while the STMXCSR instruction stores the contents ofthe register to memory.Vol. 1 10-17PROGRAMMING WITH STREAMING SIMD EXTENSIONS (SSE)10.4.6Cacheability Control, Prefetch, and Memory OrderingInstructionsSSE extensions introduce several new instructions to give programs more controlover the caching of data.
They also introduces the PREFETCHh instructions, whichprovide the ability to prefetch data to a specified cache level, and the SFENCEinstruction, which enforces program ordering on stores. These instructions aredescribed in the following sections.10.4.6.1Cacheability Control InstructionsThe following three instructions enable data from the MMX and XMM registers to bestored to memory using a non-temporal hint. The non-temporal hint directs theprocessor to when possible store the data to memory without writing the data intothe cache hierarchy. See Section 10.4.6.2, “Caching of Temporal vs.
Non-TemporalData,” for information about non-temporal stores and hints.The MOVNTQ (store quadword using non-temporal hint) instruction stores packedinteger data from an MMX register to memory, using a non-temporal hint.The MOVNTPS (store packed single-precision floating-point values using nontemporal hint) instruction stores packed floating-point data from an XMM register tomemory, using a non-temporal hint.The MASKMOVQ (store selected bytes of quadword) instruction stores selected byteintegers from an MMX register to memory, using a byte mask to selectively write theindividual bytes.
This instruction also uses a non-temporal hint.10.4.6.2Caching of Temporal vs. Non-Temporal DataData referenced by a program can be temporal (data will be used again) or nontemporal (data will be referenced once and not reused in the immediate future). Forexample, program code is generally temporal, whereas, multimedia data, such as thedisplay list in a 3-D graphics application, is often non-temporal. To make efficient useof the processor’s caches, it is generally desirable to cache temporal data and notcache non-temporal data. Overloading the processor’s caches with non-temporaldata is sometimes referred to as “polluting the caches.” The SSE and SSE2 cacheability control instructions enable a program to write non-temporal data to memoryin a manner that minimizes pollution of caches.These SSE and SSE2 non-temporal store instructions minimize cache pollutions bytreating the memory being accessed as the write combining (WC) type.
If a programspecifies a non-temporal store with one of these instructions and the destinationregion is mapped as cacheable memory (write back [WB], write through [WT] or WCmemory type), the processor will do the following:•If the memory location being written to is present in the cache hierarchy, the datain the caches is evicted.•The non-temporal data is written to memory with WC semantics.10-18 Vol. 1PROGRAMMING WITH STREAMING SIMD EXTENSIONS (SSE)See also: Chapter 10, “Memory Cache Control,” in the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 3A.Using the WC semantics, the store transaction will be weakly ordered, meaning thatthe data may not be written to memory in program order, and the store will not writeallocate (that is, the processor will not fetch the corresponding cache line into thecache hierarchy, prior to performing the store).
Also, different processor implementations may choose to collapse and combine these stores.The memory type of the region being written to can override the non-temporal hint,if the memory address specified for the non-temporal store is in uncacheablememory. Uncacheable as referred to here means that the region being written to hasbeen mapped with either an uncacheable (UC) or write protected (WP) memory type.In general, WC semantics require software to ensure coherence, with respect toother processors and other system agents (such as graphics cards). Appropriate useof synchronization and fencing must be performed for producer-consumer usagemodels.
![](https://s.studizba.com/z.php?f=/templates/si/i/noavatar.png&w=100&h=100&t=1"){kind=avatar}
