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1 8-47PROGRAMMING WITH THE X87 FPU8-48 Vol. 1CHAPTER 9PROGRAMMING WITH INTEL® MMX™ TECHNOLOGYThe Intel MMX technology was introduced into the IA-32 architecture in thePentium II processor family and Pentium processor with MMX technology. The extensions introduced in MMX technology support a single-instruction, multiple-data(SIMD) execution model that is designed to accelerate the performance of advancedmedia and communications applications.This chapter describes MMX technology.9.1OVERVIEW OF MMX TECHNOLOGYMMX technology defines a simple and flexible SIMD execution model to handle 64-bitpacked integer data. This model adds the following features to the IA-32 architecture, while maintaining backwards compatibility with all IA-32 applications andoperating-system code:••Eight new 64-bit data registers, called MMX registersThree new packed data types:— 64-bit packed byte integers (signed and unsigned)— 64-bit packed word integers (signed and unsigned)— 64-bit packed doubleword integers (signed and unsigned)•Instructions that support the new data types and to handle MMX statemanagement•Extensions to the CPUID instructionMMX technology is accessible from all the IA32-architecture execution modes(protected mode, real address mode, and virtual 8086 mode).
It does not add anynew modes to the architecture.The following sections of this chapter describe MMX technology’s programming environment, including MMX register set, data types, and instruction set. Additionalinstructions that operate on MMX registers have been added to the IA-32 architecture by the SSE/SSE2 extensions.For more information, see:•Section 10.4.4, “SSE 64-Bit SIMD Integer Instructions,” describes MMX instructions added to the IA-32 architecture with the SSE extensions.•Section 11.4.2, “SSE2 64-Bit and 128-Bit SIMD Integer Instructions,” describesMMX instructions added to the IA-32 architecture with SSE2 extensions.•Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volumes2A & 2B, give detailed descriptions of MMX instructions.Vol.
1 9-1PROGRAMMING WITH INTEL® MMX™ TECHNOLOGY•Chapter 11, “Intel® MMX™ Technology System Programming,” in the Intel® 64and IA-32 Architectures Software Developer’s Manual, Volume 3B, describes themanner in which MMX technology is integrated into the IA-32 systemprogramming model.9.2THE MMX TECHNOLOGY PROGRAMMINGENVIRONMENTFigure 9-1 shows the execution environment for MMX technology.
All MMX instructions operate on MMX registers, the general-purpose registers, and/or memory asfollows:•MMX registers — These eight registers (see Figure 9-1) are used to performoperations on 64-bit packed integer data. They are named MM0 through MM7.Address Space232-1MMX RegistersEight 64-BitGeneral-PurposeRegistersEight 32-Bit0Figure 9-1. MMX Technology Execution Environment•General-purpose registers — The eight general-purpose registers (seeFigure 3-5) are used with existing IA-32 addressing modes to address operandsin memory. (MMX registers cannot be used to address memory). Generalpurpose registers are also used to hold operands for some MMX technologyoperations. They are EAX, EBX, ECX, EDX, EBP, ESI, EDI, and ESP.9.2.1MMX Technology in 64-Bit Mode and Compatibility ModeIn compatibility mode and 64-bit mode, MMX instructions function like they do inprotected mode.
Memory operands are specified using the ModR/M, SIB encodingdescribed in Section 3.7.5.9-2 Vol. 1PROGRAMMING WITH INTEL® MMX™ TECHNOLOGY9.2.2MMX RegistersThe MMX register set consists of eight 64-bit registers (see Figure 9-2), that are usedto perform calculations on the MMX packed integer data types. Values in MMX registers have the same format as a 64-bit quantity in memory.The MMX registers have two data access modes: 64-bit access mode and 32-bitaccess mode. The 64-bit access mode is used for:••••64-bit memory accesses64-bit transfers between MMX registersAll pack, logical, and arithmetic instructionsSome unpack instructionsThe 32-bit access mode is used for:•••32-bit memory accesses32-bit transfer between general-purpose registers and MMX registersSome unpack instructions630MM7MM6MM5MM4MM3MM2MM1MM0Figure 9-2.
MMX Register SetAlthough MMX registers are defined in the IA-32 architecture as separate registers,they are aliased to the registers in the FPU data register stack (R0 through R7).See also Section 9.5, “Compatibility with x87 FPU Architecture.”9.2.3MMX Data TypesMMX technology introduced the following 64-bit data types to the IA-32 architecture(see Figure 9-3):•64-bit packed byte integers — eight packed bytesVol. 1 9-3PROGRAMMING WITH INTEL® MMX™ TECHNOLOGY••64-bit packed word integers — four packed words64-bit packed doubleword integers — two packed doublewordsMMX instructions move 64-bit packed data types (packed bytes, packed words, orpacked doublewords) and the quadword data type between MMX registers andmemory or between MMX registers in 64-bit blocks. However, when performing arithmetic or logical operations on the packed data types, MMX instructions operate inparallel on the individual bytes, words, or doublewords contained in MMX registers(see Section 9.2.5, “Single Instruction, Multiple Data (SIMD) Execution Model”).Packed Byte Integers630Packed Word Integers630Packed Doubleword Integers630Figure 9-3.
Data Types Introduced with the MMX Technology9.2.4Memory Data FormatsWhen stored in memory: bytes, words and doublewords in the packed data types arestored in consecutive addresses. The least significant byte, word, or doubleword isstored at the lowest address and the most significant byte, word, or doubleword isstored at the high address. The ordering of bytes, words, or doublewords in memoryis always little endian.
That is, the bytes with the low addresses are less significantthan the bytes with high addresses.9.2.5Single Instruction, Multiple Data (SIMD) Execution ModelMMX technology uses the single instruction, multiple data (SIMD) technique forperforming arithmetic and logical operations on bytes, words, or doublewords packedinto MMX registers (see Figure 9-4). For example, the PADDSW instruction adds 4signed word integers from one source operand to 4 signed word integers in a secondsource operand and stores 4 word integer results in a destination operand.
This SIMDtechnique speeds up software performance by allowing the same operation to becarried out on multiple data elements in parallel. MMX technology supports paralleloperations on byte, word, and doubleword data elements when contained in MMXregisters.9-4 Vol. 1PROGRAMMING WITH INTEL® MMX™ TECHNOLOGYThe SIMD execution model supported in the MMX technology directly addresses theneeds of modern media, communications, and graphics applications, which often usesophisticated algorithms that perform the same operations on a large number ofsmall data types (bytes, words, and doublewords).
For example, most audio data isrepresented in 16-bit (word) quantities. The MMX instructions can operate on 4words simultaneously with one instruction. Video and graphics information iscommonly represented as palletized 8-bit (byte) quantities. In Figure 9-4, one MMXinstruction operates on 8 bytes simultaneously.Source 1Source 2DestinationX3X2Y3Y2X1X0Y1OPOPOPX3 OP Y3X2 OP Y2X1 OP Y1Y0OPX0 OP Y0Figure 9-4. SIMD Execution Model9.3SATURATION AND WRAPAROUND MODESWhen performing integer arithmetic, an operation may result in an out-of-rangecondition, where the true result cannot be represented in the destination format.
Forexample, when performing arithmetic on signed word integers, positive overflow canoccur when the true signed result is larger than 16 bits.The MMX technology provides three ways of handling out-of-range conditions:•Wraparound arithmetic — With wraparound arithmetic, a true out-of-rangeresult is truncated (that is, the carry or overflow bit is ignored and only the leastsignificant bits of the result are returned to the destination).
Wraparoundarithmetic is suitable for applications that control the range of operands toprevent out-of-range results. If the range of operands is not controlled, however,wraparound arithmetic can lead to large errors. For example, adding two largesigned numbers can cause positive overflow and produce a negative result.•Signed saturation arithmetic — With signed saturation arithmetic, out-ofrange results are limited to the representable range of signed integers for theinteger size being operated on (see Table 9-1). For example, if positive overflowoccurs when operating on signed word integers, the result is “saturated” to7FFFH, which is the largest positive integer that can be represented in 16 bits; ifnegative overflow occurs, the result is saturated to 8000H.Vol.
1 9-5PROGRAMMING WITH INTEL® MMX™ TECHNOLOGY•Unsigned saturation arithmetic — With unsigned saturation arithmetic, outof-range results are limited to the representable range of unsigned integers forthe integer size. So, positive overflow when operating on unsigned byte integersresults in FFH being returned and negative overflow results in 00H beingreturned..Table 9-1. Data Range Limits for SaturationData TypeLower LimitHexadecimalUpper LimitDecimalHexadecimalDecimalSigned Byte80H-1287FH127Signed Word8000H-32,7687FFFH32,767Unsigned Byte00H0FFH255Unsigned Word0000H0FFFFH65,535Saturation arithmetic provides an answer for many overflow situations. For example,in color calculations, saturation causes a color to remain pure black or pure whitewithout allowing inversion.
It also prevents wraparound artifacts from entering intocomputations when range checking of source operands it not used.MMX instructions do not indicate overflow or underflow occurrence by generatingexceptions or setting flags in the EFLAGS register.9.4MMX INSTRUCTIONSThe MMX instruction set consists of 47 instructions, grouped into the following categories:••••••••Data transferArithmeticComparisonConversionUnpackingLogicalShiftEmpty MMX state instruction (EMMS)Table 9-2 gives a summary of the instructions in the MMX instruction set.
Thefollowing sections give a brief overview of the instructions within each group.9-6 Vol. 1PROGRAMMING WITH INTEL® MMX™ TECHNOLOGYNOTESThe MMX instructions described in this chapter are those instructionsthat are available in an IA-32 processor whenCPUID.01H:EDX.MMX[bit 23] = 0.Section 10.4.4, “SSE 64-Bit SIMD Integer Instructions,” and Section11.4.2, “SSE2 64-Bit and 128-Bit SIMD Integer Instructions,” listadditional instructions included with SSE/SSE2 extensions thatoperate on the MMX registers but are not considered part of the MMXinstruction set.Table 9-2. MMX Instruction Set SummaryCategoryArithmeticComparisonWraparoundAdditionPADDB, PADDW,PADDDSubtractionPSUBB, PSUBW,PSUBDMultiplicationPMULL, PMULHMultiply and AddPMADDSignedSaturationUnsigned SaturationPADDSB, PADDSW PADDUSB, PADDUSWPSUBSB, PSUBSW PSUBUSB, PSUBUSWCompare for Equal PCMPEQB,PCMPEQW,PCMPEQDCompare forPCMPGTPB,Greater ThanPCMPGTPW,PCMPGTPDConversionPackPACKSSWB,PACKSSDWUnpackUnpack HighPUNPCKHBW,PUNPCKHWD,PUNPCKHDQUnpack LowPUNPCKLBW,PUNPCKLWD,PUNPCKLDQPackedLogicalPACKUSWBFull QuadwordAndPANDAnd NotPANDNOrPORExclusive ORPXORVol.
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