Volume 1 Basic Architecture (794100), страница 56
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An empty register has a tag value of 11.NOTESThe term stack overflow originates from the situation where theprogram has loaded (pushed) eight values from memory onto thex87 FPU register stack and the next value pushed on the stack causesa stack wraparound to a register that already contains a value.The term stack underflow originates from the opposite situation.Here, a program has stored (popped) eight values from the x87 FPUregister stack to memory and the next value popped from the stackcauses stack wraparound to an empty register.When the x87 FPU detects stack overflow or underflow, it sets the IE flag (bit 0) andthe SF flag (bit 6) in the x87 FPU status word to 1. It then sets condition-code flag C1(bit 9) in the x87 FPU status word to 1 if stack overflow occurred or to 0 if stackunderflow occurred.If the invalid-operation exception is masked, the x87 FPU returns the floating point,integer, or packed decimal integer indefinite value to the destination operand,depending on the instruction being executed.
This value overwrites the destinationregister or memory location specified by the instruction.If the invalid-operation exception is not masked, a software exception handler isinvoked (see Section 8.7, “Handling x87 FPU Exceptions in Software”) and the topof-stack pointer (TOP) and source operands remain unchanged.Vol. 1 8-37PROGRAMMING WITH THE X87 FPU8.5.1.2Invalid Arithmetic Operand Exception (#IA)The x87 FPU is able to detect a variety of invalid arithmetic operations that can becoded in a program.
These operations are listed in Table 8-10. (This list includes theinvalid operations defined in IEEE Standard 754.)When the x87 FPU detects an invalid arithmetic operand, it sets the IE flag (bit 0) inthe x87 FPU status word to 1. If the invalid-operation exception is masked, the x87FPU then returns an indefinite value or QNaN to the destination operand and/or setsthe floating-point condition codes as shown in Table 8-10. If the invalid-operationexception is not masked, a software exception handler is invoked (see Section 8.7,“Handling x87 FPU Exceptions in Software”) and the top-of-stack pointer (TOP) andsource operands remain unchanged.Table 8-10. Invalid Arithmetic Operations and theMasked Responses to ThemConditionMasked ResponseAny arithmetic operation on an operand that is inan unsupported format.Return the QNaN floating-point indefinitevalue to the destination operand.Any arithmetic operation on a SNaN.Return a QNaN to the destination operand (seeTable 4-7).Ordered compare and test operations: one or bothoperands are NaNs.Set the condition code flags (C0, C2, and C3) inthe x87 FPU status word or the CF, PF, and ZFflags in the EFLAGS register to 111B (notcomparable).Addition: operands are opposite-signed infinities.Subtraction: operands are like-signed infinities.Return the QNaN floating-point indefinitevalue to the destination operand.Multiplication: ∞ by 0; 0 by ∞ .Return the QNaN floating-point indefinitevalue to the destination operand.Division: ∞ by ∞ ; 0 by 0.Return the QNaN floating-point indefinitevalue to the destination operand.Remainder instructions FPREM, FPREM1: modulus(divisor) is 0 or dividend is ∞ .Return the QNaN floating-point indefinite;clear condition code flag C2 to 0.Trigonometric instructions FCOS, FPTAN, FSIN,FSINCOS: source operand is ∞ .Return the QNaN floating-point indefinite;clear condition code flag C2 to 0.FSQRT: negative operand (except FSQRT (–0) = –0); FYL2X: negative operand (except FYL2X (–0) =–∞); FYL2XP1: operand more negative than –1.Return the QNaN floating-point indefinitevalue to the destination operand.FBSTP: Converted value cannot be represented in18 decimal digits, or source value is an SNaN,QNaN, ± ∞ , or in an unsupported format.Store packed BCD integer indefinite value inthe destination operand.8-38 Vol.
1PROGRAMMING WITH THE X87 FPUTable 8-10. Invalid Arithmetic Operations and theMasked Responses to Them (Contd.)FIST/FISTP: Converted value exceedsrepresentable integer range of the destinationoperand, or source value is an SNaN, QNaN, ±∞, orin an unsupported format.Store integer indefinite value in thedestination operand.FXCH: one or both registers are tagged empty.Load empty registers with the QNaN floatingpoint indefinite value, then perform theexchange.Normally, when one or both of the source operands is a QNaN (and neither is anSNaN or in an unsupported format), an invalid-operand exception is not generated.An exception to this rule is most of the compare instructions (such as the FCOM andFCOMI instructions) and the floating-point to integer conversion instructions(FIST/FISTP and FBSTP). With these instructions, a QNaN source operand willgenerate an invalid-operand exception.8.5.2Denormal Operand Exception (#D)The x87 FPU signals the denormal-operand exception under the following conditions:•If an arithmetic instruction attempts to operate on a denormal operand (seeSection 4.8.3.2, “Normalized and Denormalized Finite Numbers”).•If an attempt is made to load a denormal single-precision or double-precisionfloating-point value into an x87 FPU register.
(If the denormal value being loadedis a double extended-precision floating-point value, the denormal-operandexception is not reported.)The flag (DE) for this exception is bit 1 of the x87 FPU status word, and the mask bit(DM) is bit 1 of the x87 FPU control word.When a denormal-operand exception occurs and the exception is masked, the x87FPU sets the DE flag, then proceeds with the instruction. The denormal operand insingle- or double-precision floating-point format is automatically normalized whenconverted to the double extended-precision floating-point format.
Subsequent operations will benefit from the additional precision of the internal double extended-precision floating-point format.When a denormal-operand exception occurs and the exception is not masked, the DEflag is set and a software exception handler is invoked (see Section 8.7, “Handlingx87 FPU Exceptions in Software”). The top-of-stack pointer (TOP) and source operands remain unchanged.For additional information about the denormal-operation exception, see Section4.9.1.2, “Denormal Operand Exception (#D).”Vol.
1 8-39PROGRAMMING WITH THE X87 FPU8.5.3Divide-By-Zero Exception (#Z)The x87 FPU reports a floating-point divide-by-zero exception whenever an instruction attempts to divide a finite non-zero operand by 0. The flag (ZE) for this exceptionis bit 2 of the x87 FPU status word, and the mask bit (ZM) is bit 2 of the x87 FPUcontrol word. The FDIV, FDIVP, FDIVR, FDIVRP, FIDIV, and FIDIVR instructions andthe other instructions that perform division internally (FYL2X and FXTRACT) canreport the divide-by-zero exception.When a divide-by-zero exception occurs and the exception is masked, the x87 FPUsets the ZE flag and returns the values shown in Table 8-10.
If the divide-by-zeroexception is not masked, the ZE flag is set, a software exception handler is invoked(see Section 8.7, “Handling x87 FPU Exceptions in Software”), and the top-of-stackpointer (TOP) and source operands remain unchanged.Table 8-11.
Divide-By-Zero Conditions and the Masked Responses to ThemConditionMasked ResponseDivide or reverse divide operationwith a 0 divisor.Returns an ∞ signed with the exclusive OR of the sign of thetwo operands to the destination operand.FYL2X instruction.Returns an ∞ signed with the opposite sign of the non-zerooperand to the destination operand.FXTRACT instruction.ST(1) is set to –∞; ST(0) is set to 0 with the same sign as thesource operand.8.5.4Numeric Overflow Exception (#O)The x87 FPU reports a floating-point numeric overflow exception (#O) whenever therounded result of an arithmetic instruction exceeds the largest allowable finite valuethat will fit into the floating-point format of the destination operand. (See Section4.9.1.4, “Numeric Overflow Exception (#O),” for additional information about thenumeric overflow exception.)When using the x87 FPU, numeric overflow can occur on arithmetic operations wherethe result is stored in an x87 FPU data register.
It can also occur on store floatingpoint operations (using the FST and FSTP instructions), where a within-range valuein a data register is stored in memory in a single-precision or double-precisionfloating-point format. The numeric overflow exception cannot occur when storingvalues in an integer or BCD integer format. Instead, the invalid-arithmetic-operandexception is signaled.The flag (OE) for the numeric-overflow exception is bit 3 of the x87 FPU status word,and the mask bit (OM) is bit 3 of the x87 FPU control word.When a numeric-overflow exception occurs and the exception is masked, the x87FPU sets the OE flag and returns one of the values shown in Table 4-10.
The valuereturned depends on the current rounding mode of the x87 FPU (see Section 8.1.5.3,“Rounding Control Field”).8-40 Vol. 1PROGRAMMING WITH THE X87 FPUThe action that the x87 FPU takes when numeric overflow occurs and the numericoverflow exception is not masked, depends on whether the instruction is supposed tostore the result in memory or on the register stack.•Destination is a memory location — The OE flag is set and a softwareexception handler is invoked (see Section 8.7, “Handling x87 FPU Exceptions inSoftware”).
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