Volume 1 Basic Architecture (794100), страница 51
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The FSTSW AX instruction moves the x87 FPU status word into the AX register.2. The SAHF instruction copies the upper 8 bits of the AX register, which includes thecondition code flags, into the lower 8 bits of the EFLAGS register.When the condition code flags have been loaded into the EFLAGS register, conditionaljumps or conditional moves can be performed based on the new settings of thestatus flags in the EFLAGS register.Vol. 1 8-9PROGRAMMING WITH THE X87 FPUx87 FPU Status Word15Condition StatusFlagCodeC0C1C2C3CF(none)PFZFC30C C C2 1 0FSTSW AX InstructionAX Register15C30C C C2 1 0SAHF Instruction31EFLAGS Register70ZFPCF 1 FFigure 8-5. Moving the Condition Codes to the EFLAGS RegisterThe new mechanism is available beginning with the P6 family processors. Using thismechanism, the new floating-point compare and set EFLAGS instructions (FCOMI,FCOMIP, FUCOMI, and FUCOMIP) compare two floating-point values and set the ZF,PF, and CF flags in the EFLAGS register directly.
A single instruction thus replaces thethree instructions required by the old mechanism.Note also that the FCMOVcc instructions (also new in the P6 family processors) allowconditional moves of floating-point values (values in the x87 FPU data registers)based on the setting of the status flags (ZF, PF, and CF) in the EFLAGS register. Theseinstructions eliminate the need for an IF statement to perform conditional moves offloating-point values.8.1.5x87 FPU Control WordThe 16-bit x87 FPU control word (see Figure 8-6) controls the precision of the x87FPU and rounding method used. It also contains the x87 FPU floating-point exceptionmask bits. The control word is cached in the x87 FPU control register. The contents ofthis register can be loaded with the FLDCW instruction and stored in memory with theFSTCW/FNSTCW instructions.8-10 Vol.
1PROGRAMMING WITH THE X87 FPUInfinity ControlRounding ControlPrecision Control15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0XRCPCP U O Z D IM M M M M MException MasksPrecisionUnderflowOverflowZero DivideDenormal OperandInvalid OperationReservedFigure 8-6. x87 FPU Control WordWhen the x87 FPU is initialized with either an FINIT/FNINIT or FSAVE/FNSAVEinstruction, the x87 FPU control word is set to 037FH, which masks all floating-pointexceptions, sets rounding to nearest, and sets the x87 FPU precision to 64 bits.8.1.5.1x87 FPU Floating-Point Exception Mask BitsThe exception-flag mask bits (bits 0 through 5 of the x87 FPU control word) mask the6 floating-point exception flags in the x87 FPU status word. When one of these maskbits is set, its corresponding x87 FPU floating-point exception is blocked from beinggenerated.8.1.5.2Precision Control FieldThe precision-control (PC) field (bits 8 and 9 of the x87 FPU control word) determinesthe precision (64, 53, or 24 bits) of floating-point calculations made by the x87 FPU(see Table 8-2).
The default precision is double extended precision, which uses thefull 64-bit significand available with the double extended-precision floating-pointformat of the x87 FPU data registers. This setting is best suited for most applications,because it allows applications to take full advantage of the maximum precision available with the x87 FPU data registers.Vol. 1 8-11PROGRAMMING WITH THE X87 FPUTable 8-2. Precision Control Field (PC)PrecisionPC FieldSingle Precision (24 bits)00BReserved01BDouble Precision (53 bits)10BDouble Extended Precision (64 bits)11BThe double precision and single precision settings reduce the size of the significand to53 bits and 24 bits, respectively. These settings are provided to support IEEE Standard 754 and to provide compatibility with the specifications of certain existingprogramming languages.
Using these settings nullifies the advantages of the doubleextended-precision floating-point format's 64-bit significand length. When reducedprecision is specified, the rounding of the significand value clears the unused bits onthe right to zeros.The precision-control bits only affect the results of the following floating-pointinstructions: FADD, FADDP, FIADD, FSUB, FSUBP, FISUB, FSUBR, FSUBRP, FISUBR,FMUL, FMULP, FIMUL, FDIV, FDIVP, FIDIV, FDIVR, FDIVRP, FIDIVR, and FSQRT.8.1.5.3Rounding Control FieldThe rounding-control (RC) field of the x87 FPU control register (bits 10 and 11)controls how the results of x87 FPU floating-point instructions are rounded.
SeeSection 4.8.4, “Rounding,” for a discussion of rounding of floating-point values; SeeSection 4.8.4.1, “Rounding Control (RC) Fields”, for the encodings of the RC field.8.1.6Infinity Control FlagThe infinity control flag (bit 12 of the x87 FPU control word) is provided for compatibility with the Intel 287 Math Coprocessor; it is not meaningful for later version x87FPU coprocessors or IA-32 processors. See Section 4.8.3.3, “Signed Infinities,” forinformation on how the x87 FPUs handle infinity values.8.1.7x87 FPU Tag WordThe 16-bit tag word (see Figure 8-7) indicates the contents of each the 8 registers inthe x87 FPU data-register stack (one 2-bit tag per register). The tag codes indicatewhether a register contains a valid number, zero, or a special floating-point number(NaN, infinity, denormal, or unsupported format), or whether it is empty.
The x87FPU tag word is cached in the x87 FPU in the x87 FPU tag word register. When the x87FPU is initialized with either an FINIT/FNINIT or FSAVE/FNSAVE instruction, the x87FPU tag word is set to FFFFH, which marks all the x87 FPU data registers as empty.8-12 Vol. 1PROGRAMMING WITH THE X87 FPU.150TAG(7)TAG(6)TAG(5)TAG(4)TAG(3)TAG(2)TAG(1)TAG(0)TAG Values00 — Valid01 — Zero10 — Special: invalid (NaN, unsupported), infinity, or denormal11 — EmptyFigure 8-7. x87 FPU Tag WordEach tag in the x87 FPU tag word corresponds to a physical register (numbers 0through 7). The current top-of-stack (TOP) pointer stored in the x87 FPU status wordcan be used to associate tags with registers relative to ST(0).The x87 FPU uses the tag values to detect stack overflow and underflow conditions(see Section 8.5.1.1, “Stack Overflow or Underflow Exception (#IS)”).Application programs and exception handlers can use this tag information to checkthe contents of an x87 FPU data register without performing complex decoding of theactual data in the register.
To read the tag register, it must be stored in memory usingeither the FSTENV/FNSTENV or FSAVE/FNSAVE instructions. The location of the tagword in memory after being saved with one of these instructions is shown in Figures8-9 through 8-12.Software cannot directly load or modify the tags in the tag register.
The FLDENV andFRSTOR instructions load an image of the tag register into the x87 FPU; however, thex87 FPU uses those tag values only to determine if the data registers are empty(11B) or non-empty (00B, 01B, or 10B).If the tag register image indicates that a data register is empty, the tag in the tagregister for that data register is marked empty (11B); if the tag register image indicates that the data register is non-empty, the x87 FPU reads the actual value in thedata register and sets the tag for the register accordingly.
This action prevents aprogram from setting the values in the tag register to incorrectly represent the actualcontents of non-empty data registers.8.1.8x87 FPU Instruction and Data (Operand) PointersThe x87 FPU stores pointers to the instruction and data (operand) for the last noncontrol instruction executed. These pointers are stored in two 48-bit registers: thex87 FPU instruction pointer and x87 FPU operand (data) pointer registers (seeFigure 8-1). (These pointers are saved to provide state information for exceptionhandlers.)Vol.
1 8-13PROGRAMMING WITH THE X87 FPUNote that the value in the x87 FPU data pointer register is always a pointer to amemory operand, If the last non-control instruction that was executed did not havea memory operand, the value in the data pointer register is undefined (reserved).The contents of the x87 FPU instruction and data pointer registers remain unchangedwhen any of the control instructions (FINIT/FNINIT, FCLEX/FNCLEX, FLDCW,FSTCW/FNSTCW, FSTSW/FNSTSW, FSTENV/FNSTENV, FLDENV, FSAVE/FNSAVE,FRSTOR, and WAIT/FWAIT) are executed.The pointers stored in the x87 FPU instruction and data pointer registers consist of anoffset (stored in bits 0 through 31) and a segment selector (stored in bits 32through 47).These registers can be accessed by the FSTENV/FNSTENV, FLDENV, FINIT/FNINIT,FSAVE/FNSAVE, FRSTOR, FXSAVE, and FXRSTOR instructions.
The FINIT/FNINIT andFSAVE/FNSAVE instructions clear these registers.For all the x87 FPUs and NPXs except the 8087, the x87 FPU instruction pointer pointsto any prefixes that preceded the instruction. For the 8087, the x87 FPU instructionpointer points only to the actual opcode.8.1.9Last Instruction OpcodeThe x87 FPU stores the opcode of the last non-control instruction executed in an11-bit x87 FPU opcode register. (This information provides state information forexception handlers.) Only the first and second opcode bytes (after all prefixes) arestored in the x87 FPU opcode register.
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