Volume 1 Basic Architecture (794100), страница 49
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These instructions are only used when an operating systemor executive is using the segmented or the real-address mode memory model.For the purpose of this discussion, these instructions are divided subordinatesubgroups of instructions that allow:••••Segment-register load and storeFar control transfersSoftware interrupt callsHandling of far pointers7.3.16.1Segment-Register Load and Store InstructionsThe MOV instruction (introduced in Section 7.3.1.1, “General Data MovementInstructions”) and the PUSH and POP instructions (introduced in Section 7.3.1.4,“Stack Manipulation Instructions”) can transfer 16-bit segment selectors to and fromVol.
1 7-31PROGRAMMING WITH GENERAL-PURPOSE INSTRUCTIONSsegment registers (DS, ES, FS, GS, and SS). The transfers are always made to orfrom a segment register and a general-purpose register or memory. Transfersbetween segment registers are not supported.The POP and MOV instructions cannot place a value in the CS register. Only the farcontrol-transfer versions of the JMP, CALL, and RET instructions (see Section7.3.16.2, “Far Control Transfer Instructions”) affect the CS register directly.7.3.16.2Far Control Transfer InstructionsThe JMP and CALL instructions (see Section 7.3.8, “Control Transfer Instructions”)both accept a far pointer as a source operand to transfer program control to asegment other than the segment currently being pointed to by the CS register. Whena far call is made with the CALL instruction, the current values of the EIP and CSregisters are both pushed on the stack.The RET instruction (see “Call and return instructions” on page 7-22) can be used toexecute a far return.
Here, program control is transferred from a code segment thatcontains a called procedure back to the code segment that contained the callingprocedure. The RET instruction restores the values of the CS and EIP registers for thecalling procedure from the stack.7.3.16.3Software Interrupt InstructionsThe software interrupt instructions INT, INTO, BOUND, and IRET (see Section7.3.8.4, “Software Interrupt Instructions”) can also call and return from interruptand exception handler procedures that are located in a code segment other than thecurrent code segment.
With these instructions, however, the switching of codesegments is handled transparently from the application program.7.3.16.4Load Far Pointer InstructionsThe load far pointer instructions LDS (load far pointer using DS), LES (load farpointer using ES), LFS (load far pointer using FS), LGS (load far pointer using GS),and LSS (load far pointer using SS) load a far pointer from memory into a segmentregister and a general-purpose general register. The segment selector part of the farpointer is loaded into the selected segment register and the offset is loaded into theselected general-purpose register.7.3.17Miscellaneous InstructionsThe following instructions perform operations that are of interest to applicationsprogrammers. For the purpose of this discussion, these instructions are furtherdivided into subordinate subgroups of instructions that provide for:••Address computationsTable lookup7-32 Vol.
1PROGRAMMING WITH GENERAL-PURPOSE INSTRUCTIONS••Processor identificationNOP and undefined instruction entry7.3.17.1Address Computation InstructionThe LEA (load effective address) instruction computes the effective address inmemory (offset within a segment) of a source operand and places it in a generalpurpose register. This instruction can interpret any of the processor’s addressingmodes and can perform any indexing or scaling that may be needed. It is especiallyuseful for initializing the ESI or EDI registers before the execution of string instructions or for initializing the EBX register before an XLAT instruction.7.3.17.2Table Lookup InstructionsThe XLAT and XLATB (table lookup) instructions replace the contents of the ALregister with a byte read from a translation table in memory. The initial value in theAL register is interpreted as an unsigned index into the translation table.
This indexis added to the contents of the EBX register (which contains the base address of thetable) to calculate the address of the table entry. These instructions are used forapplications such as converting character codes from one alphabet into another (forexample, an ASCII code could be used to look up its EBCDIC equivalent in a table).7.3.17.3Processor Identification InstructionThe CPUID (processor identification) instruction returns information about theprocessor on which the instruction is executed.7.3.17.4No-Operation and Undefined InstructionsThe NOP (no operation) instruction increments the EIP register to point at the nextinstruction, but affects nothing else.The UD2 (undefined) instruction generates an invalid opcode exception.
Intelreserves the opcode for this instruction for this function. The instruction is providedto allow software to test an invalid opcode exception handler.Vol. 1 7-33PROGRAMMING WITH GENERAL-PURPOSE INSTRUCTIONS7-34 Vol. 1CHAPTER 8PROGRAMMING WITH THE X87 FPUThe x87 Floating-Point Unit (FPU) provides high-performance floating-pointprocessing capabilities for use in graphics processing, scientific, engineering, andbusiness applications. It supports the floating-point, integer, and packed BCD integerdata types and the floating-point processing algorithms and exception handlingarchitecture defined in the IEEE Standard 754 for Binary Floating-Point Arithmetic.This chapter describes the x87 FPU’s execution environment and instruction set.
Italso provides exception handling information that is specific to the x87 FPU. Refer tothe following chapters or sections of chapters for additional information about x87FPU instructions and floating-point operations:•Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volumes2A & 2B, provide detailed descriptions of x87 FPU instructions.•Section 4.2.2, “Floating-Point Data Types,” Section 4.2.1.2, “Signed Integers,”and Section 4.7, “BCD and Packed BCD Integers,” describe the floating-point,integer, and BCD data types.•Section 4.9, “Overview of Floating-Point Exceptions,” Section 4.9.1, “FloatingPoint Exception Conditions,” and Section 4.9.2, “Floating-Point ExceptionPriority,” give an overview of the floating-point exceptions that the x87 FPU candetect and report.8.1X87 FPU EXECUTION ENVIRONMENTThe x87 FPU represents a separate execution environment within the IA-32 architecture (see Figure 8-1).
This execution environment consists of eight data registers(called the x87 FPU data registers) and the following special-purpose registers:••••••Status registerControl registerTag word registerLast instruction pointer registerLast data (operand) pointer registerOpcode registerThese registers are described in the following sections.The x87 FPU executes instructions from the processor’s normal instruction stream.The state of the x87 FPU is independent from the state of the basic execution environment and from the state of SSE/SSE2/SSE3 extensions.However, the x87 FPU and Intel MMX technology share state because the MMX registers are aliased to the x87 FPU data registers.
Therefore, when writing code that usesVol. 1 8-1PROGRAMMING WITH THE X87 FPUx87 FPU and MMX instructions, the programmer must explicitly manage the x87 FPUand MMX state (see Section 9.5, “Compatibility with x87 FPU Architecture”).8.1.1x87 FPU in 64-Bit Mode and Compatibility ModeIn compatibility mode and 64-bit mode, x87 FPU instructions function like they do inprotected mode. Memory operands are specified using the ModR/M, SIB encodingthat is described in Section 3.7.5, “Specifying an Offset.”8.1.2x87 FPU Data RegistersThe x87 FPU data registers (shown in Figure 8-1) consist of eight 80-bit registers.Values are stored in these registers in the double extended-precision floating-pointformat shown in Figure 4-3.
When floating-point, integer, or packed BCD integervalues are loaded from memory into any of the x87 FPU data registers, the values areautomatically converted into double extended-precision floating-point format (if theyare not already in that format).
When computation results are subsequently transferred back into memory from any of the x87 FPU registers, the results can be left inthe double extended-precision floating-point format or converted back into a shorterfloating-point format, an integer format, or the packed BCD integer format. (SeeSection 8.2, “x87 FPU Data Types,” for a description of the data types operated on bythe x87 FPU.)8-2 Vol. 1PROGRAMMING WITH THE X87 FPUData RegistersSign79 78R7064 63ExponentSignificandR6R5R4R3R2R1R0015470ControlRegisterLast Instruction PointerStatusRegisterLast Data (Operand) PointerTagRegister100OpcodeFigure 8-1.
x87 FPU Execution EnvironmentThe x87 FPU instructions treat the eight x87 FPU data registers as a register stack (seeFigure 8-2). All addressing of the data registers is relative to the register on the top ofthe stack. The register number of the current top-of-stack register is stored in theTOP (stack TOP) field in the x87 FPU status word. Load operations decrement TOP byone and load a value into the new top-of-stack register, and store operations storethe value from the current TOP register in memory and then increment TOP by one.(For the x87 FPU, a load operation is equivalent to a push and a store operation isequivalent to a pop.) Note that load and store operations are also available that donot push and pop the stack.Vol.
1 8-3PROGRAMMING WITH THE X87 FPUFPU Data Register Stack76GrowthStack 54ST(1)Top3ST(0)011BST(2)210Figure 8-2. x87 FPU Data Register StackIf a load operation is performed when TOP is at 0, register wraparound occurs andthe new value of TOP is set to 7. The floating-point stack-overflow exception indicateswhen wraparound might cause an unsaved value to be overwritten (see Section8.5.1.1, “Stack Overflow or Underflow Exception (#IS)”).Many floating-point instructions have several addressing modes that permit theprogrammer to implicitly operate on the top of the stack, or to explicitly operate onspecific registers relative to the TOP.
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