Volume 1 Basic Architecture (794100), страница 48
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1 7-27PROGRAMMING WITH GENERAL-PURPOSE INSTRUCTIONSat higher addresses and work toward lower ones, or they can begin at loweraddresses and work toward higher ones. The DF flag in the EFLAGS register controlswhether the registers are incremented (DF = 0) or decremented (DF = 1). The STDand CLD instructions set and clear this flag, respectively.The following repeat prefixes can be used in conjunction with a count in the ECXregister to cause a string instruction to repeat:•••REP — Repeat while the ECX register not zero.REPE/REPZ — Repeat while the ECX register not zero and the ZF flag is set.REPNE/REPNZ — Repeat while the ECX register not zero and the ZF flag is clear.When a string instruction has a repeat prefix, the operation executes until one of thetermination conditions specified by the prefix is satisfied.
The REPE/REPZ andREPNE/REPNZ prefixes are used only with the CMPS and SCAS instructions. Also,note that a REP STOS instruction is the fastest way to initialize a large block ofmemory.7.3.10String Operations in 64-Bit ModeThe behavior of MOVS (Move String), CMPS (Compare string), SCAS (Scan string),LODS (Load string), and STOS (Store string) instructions in 64-bit mode is similar totheir behavior in non-64-bit modes, with the following differences:•The source operand is specified by RSI or DS:ESI, depending on the address sizeattribute of the operation.•The destination operand is specified by RDI or DS:EDI, depending on the addresssize attribute of the operation.•Operation on 64-bit data is supported by using the REX.W prefix.7.3.10.1Repeating String Operations in 64-bit ModeWhen using REP prefixes for string operations in 64-bit mode, the repeat count isspecified by RCX or ECX (depending on the address size attribute of the operation).The default address size is 64 bits.7.3.11I/O InstructionsThe IN (input from port to register), INS (input from port to string), OUT (outputfrom register to port), and OUTS (output string to port) instructions move databetween the processor’s I/O ports and either a register or memory.The register I/O instructions (IN and OUT) move data between an I/O port and theEAX register (32-bit I/O), the AX register (16-bit I/O), or the AL (8-bit I/O) register.The I/O port being read or written to is specified with an immediate operand or anaddress in the DX register.7-28 Vol.
1PROGRAMMING WITH GENERAL-PURPOSE INSTRUCTIONSThe block I/O instructions (INS and OUTS) instructions move blocks of data (strings)between an I/O port and memory. These instructions operate similar to the stringinstructions (see Section 7.3.9, “String Operations”). The ESI and EDI registers areused to specify string elements in memory and the repeat prefixes (REP) are used torepeat the instructions to implement block moves. The assembler recognizes thefollowing alternate mnemonics for these instructions: INSB (input byte), INSW (inputword), and INSD (input doubleword), and OUTB (output byte), OUTW (output word),and OUTD (output doubleword).The INS and OUTS instructions use an address in the DX register to specify the I/Oport to be read or written to.7.3.12I/O Instructions in 64-Bit ModeFor I/O instructions to and from memory, the differences in 64-bit mode are:•The source operand is specified by RSI or DS:ESI, depending on the address sizeattribute of the operation.•The destination operand is specified by RDI or DS:EDI, depending on the addresssize attribute of the operation.•Operation on 64-bit data is not encodable and REX prefixes are silently ignored.7.3.13Enter and Leave InstructionsThe ENTER and LEAVE instructions provide machine-language support for procedurecalls in block-structured languages, such as C and Pascal.
These instructions and thecall and return mechanism that they support are described in detail in Section 6.5,“Procedure Calls for Block-Structured Languages”.7.3.14Flag Control (EFLAG) InstructionsThe Flag Control (EFLAG) instructions allow the state of selected flags in the EFLAGSregister to be read or modified. For the purpose of this discussion, these instructionsare further divided subordinate subgroups of instructions that manipulate:•••Carry and direction flagsThe EFLAGS registerInterrupt flags7.3.14.1Carry and Direction Flag InstructionsThe STC (set carry flag), CLC (clear carry flag), and CMC (complement carry flag)instructions allow the CF flags in the EFLAGS register to be modified directly. Theyare typically used to initialize the CF flag to a known state before an instruction thatVol.
1 7-29PROGRAMMING WITH GENERAL-PURPOSE INSTRUCTIONSuses the flag in an operation is executed. They are also used in conjunction with therotate-with-carry instructions (RCL and RCR).The STD (set direction flag) and CLD (clear direction flag) instructions allow the DFflag in the EFLAGS register to be modified directly. The DF flag determines the direction in which index registers ESI and EDI are stepped when executing stringprocessing instructions. If the DF flag is clear, the index registers are incrementedafter each iteration of a string instruction; if the DF flag is set, the registers aredecremented.7.3.14.2EFLAGS Transfer InstructionsThe EFLAGS transfer instructions allow groups of flags in the EFLAGS register to becopied to a register or memory or be loaded from a register or memory.The LAHF (load AH from flags) and SAHF (store AH into flags) instructions operate onfive of the EFLAGS status flags (SF, ZF, AF, PF, and CF).
The LAHF instruction copiesthe status flags to bits 7, 6, 4, 2, and 0 of the AH register, respectively. The contentsof the remaining bits in the register (bits 5, 3, and 1) are undefined, and the contentsof the EFLAGS register remain unchanged. The SAHF instruction copies bits 7, 6, 4,2, and 0 from the AH register into the SF, ZF, AF, PF, and CF flags, respectively in theEFLAGS register.The PUSHF (push flags), PUSHFD (push flags double), POPF (pop flags), and POPFD(pop flags double) instructions copy the flags in the EFLAGS register to and from thestack.
The PUSHF instruction pushes the lower word of the EFLAGS register onto thestack (see Figure 7-11). The PUSHFD instruction pushes the entire EFLAGS registeronto the stack (with the RF and VM flags read as clear).PUSHFD/POPFDPUSHF/POPF31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0V VA V R 0 N0 0 0 0 0 0 0 0 0 0 I I ITC M FDP FIOPLO D I T S ZPCAF F F F F F 0 F 0 F 1 FFigure 7-11. Flags Affected by the PUSHF, POPF, PUSHFD, and POPFD InstructionsThe POPF instruction pops a word from the stack into the EFLAGS register. Only bits11, 10, 8, 7, 6, 4, 2, and 0 of the EFLAGS register are affected with all uses of thisinstruction.
If the current privilege level (CPL) of the current code segment is 0 (mostprivileged), the IOPL bits (bits 13 and 12) also are affected. If the I/O privilege level(IOPL) is greater than or equal to the CPL, numerically, the IF flag (bit 9) also isaffected.7-30 Vol. 1PROGRAMMING WITH GENERAL-PURPOSE INSTRUCTIONSThe POPFD instruction pops a doubleword into the EFLAGS register. This instructioncan change the state of the AC bit (bit 18) and the ID bit (bit 21), as well as the bitsaffected by a POPF instruction.
The restrictions for changing the IOPL bits and the IFflag that were given for the POPF instruction also apply to the POPFD instruction.7.3.14.3Interrupt Flag InstructionsThe STI (set interrupt flag) and CTI (clear interrupt flag) instructions allow the interrupt IF flag in the EFLAGS register to be modified directly. The IF flag controls theservicing of hardware-generated interrupts (those received at the processor’s INTRpin). If the IF flag is set, the processor services hardware interrupts; if the IF flag isclear, hardware interrupts are masked.The ability to execute these instructions depends on the operating mode of theprocessor and the current privilege level (CPL) of the program or task attempting toexecute these instructions.7.3.15Flag Control (RFLAG) Instructions in 64-Bit ModeIn 64-bit mode, the LAHF and SAHF instructions are supported ifCPUID.80000001H:ECX.LAHF-SAHF[bit 0] = 1.PUSHF and POPF behave the same in 64-bit mode as in non-64-bit mode.
PUSHFDalways pushes 64-bit RFLAGS onto the stack (with the RF and VM flags read as clear).POPFD always pops a 64-bit value from the top of the stack and loads the lower 32bits into RFLAGS. It then zero extends the upper bits of RFLAGS.7.3.16Segment Register InstructionsThe processor provides a variety of instructions that address the segment registersof the processor directly.
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