Volume 1 Basic Architecture (794100), страница 43
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1PROGRAMMING WITH GENERAL-PURPOSE INSTRUCTIONSTable 7-2 shows mnemonics for CMOVcc instructions and the conditions being testedfor each instruction. The condition code mnemonics are appended to the letters“CMOV” to form the mnemonics for CMOVcc instructions. The instructions listed inTable 7-2 as pairs (for example, CMOVA/CMOVNBE) are alternate names for thesame instruction. The assembler provides these alternate names to make it easier toread program listings.CMOVcc instructions are useful for optimizing small IF constructions. They also helpeliminate branching overhead for IF statements and the possibility of branch mispredictions by the processor.These conditional move instructions are supported in the P6 family, Pentium 4, andIntel Xeon processors.
Software can check if CMOVcc instructions are supported bychecking the processor’s feature information with the CPUID instruction.7.3.1.2Exchange InstructionsThe exchange instructions swap the contents of one or more operands and, in somecases, perform additional operations such as asserting the LOCK signal or modifyingflags in the EFLAGS register.The XCHG (exchange) instruction swaps the contents of two operands.
This instruction takes the place of three MOV instructions and does not require a temporary location to save the contents of one operand location while the other is being loaded.When a memory operand is used with the XCHG instruction, the processor’s LOCKsignal is automatically asserted. This instruction is thus useful for implementingsemaphores or similar data structures for process synchronization.
See “BusLocking” in Chapter 7, “Multiple-Processor Management,” of the Intel® 64 and IA-32Architectures Software Developer’s Manual, Volume 3A, for more information on buslocking.The BSWAP (byte swap) instruction reverses the byte order in a 32-bit registeroperand. Bit positions 0 through 7 are exchanged with 24 through 31, and bit positions 8 through 15 are exchanged with 16 through 23. Executing this instructiontwice in a row leaves the register with the same value as before.
The BSWAP instruction is useful for converting between “big-endian” and “little-endian” data formats.This instruction also speeds execution of decimal arithmetic. (The XCHG instructioncan be used to swap the bytes in a word.)Vol. 1 7-5PROGRAMMING WITH GENERAL-PURPOSE INSTRUCTIONSTable 7-2. Conditional Move InstructionsInstruction MnemonicStatus Flag StatesCondition DescriptionCMOVA/CMOVNBE(CF or ZF) = 0Above/not below or equalCMOVAE/CMOVNBCF = 0Above or equal/not belowCMOVNCCF = 0Not carryCMOVB/CMOVNAECF = 1Below/not above or equalCMOVCCF = 1CarryCMOVBE/CMOVNA(CF or ZF) = 1Below or equal/not aboveCMOVE/CMOVZZF = 1Equal/zeroUnsigned Conditional MovesCMOVNE/CMOVNZZF = 0Not equal/not zeroCMOVP/CMOVPEPF = 1Parity/parity evenCMOVNP/CMOVPOPF = 0Not parity/parity oddCMOVGE/CMOVNL(SF xor OF) = 0Greater or equal/not lessCMOVL/CMOVNGE(SF xor OF) = 1Less/not greater or equalCMOVLE/CMOVNG((SF xor OF) or ZF) = 1Less or equal/not greaterCMOVOOF = 1OverflowCMOVNOOF = 0Not overflowSigned Conditional MovesCMOVSSF = 1Sign (negative)CMOVNSSF = 0Not sign (non-negative)The XADD (exchange and add) instruction swaps two operands and then stores thesum of the two operands in the destination operand.
The status flags in the EFLAGSregister indicate the result of the addition. This instruction can be combined with theLOCK prefix (see “LOCK—Assert LOCK# Signal Prefix” in Chapter 3, “Instruction SetReference, A-M,” of the Intel® 64 and IA-32 Architectures Software Developer’sManual, Volume 2A) in a multiprocessing system to allow multiple processors toexecute one DO loop.The CMPXCHG (compare and exchange) and CMPXCHG8B (compare and exchange8 bytes) instructions are used to synchronize operations in systems that usemultiple processors.
The CMPXCHG instruction requires three operands: a sourceoperand in a register, another source operand in the EAX register, and a destinationoperand. If the values contained in the destination operand and the EAX register areequal, the destination operand is replaced with the value of the other sourceoperand (the value not in the EAX register). Otherwise, the original value of thedestination operand is loaded in the EAX register. The status flags in the EFLAGS7-6 Vol.
1PROGRAMMING WITH GENERAL-PURPOSE INSTRUCTIONSregister reflect the result that would have been obtained by subtracting the destination operand from the value in the EAX register.The CMPXCHG instruction is commonly used for testing and modifying semaphores.It checks to see if a semaphore is free. If the semaphore is free, it is marked allocated; otherwise it gets the ID of the current owner.
This is all done in one uninterruptible operation. In a single-processor system, the CMPXCHG instructioneliminates the need to switch to protection level 0 (to disable interrupts) beforeexecuting multiple instructions to test and modify a semaphore.For multiple processor systems, CMPXCHG can be combined with the LOCK prefix toperform the compare and exchange operation atomically. (See “Locked Atomic Operations” in Chapter 7, “Multiple-Processor Management,” of the Intel® 64 and IA-32Architectures Software Developer’s Manual, Volume 3A, for more information onatomic operations.)The CMPXCHG8B instruction also requires three operands: a 64-bit value inEDX:EAX, a 64-bit value in ECX:EBX, and a destination operand in memory.
Theinstruction compares the 64-bit value in the EDX:EAX registers with the destinationoperand. If they are equal, the 64-bit value in the ECX:EBX register is stored in thedestination operand. If the EDX:EAX register and the destination are not equal, thedestination is loaded in the EDX:EAX register. The CMPXCHG8B instruction can becombined with the LOCK prefix to perform the operation atomically.7.3.1.3Exchange Instructions in 64-Bit ModeThe CMPXCHG16B instruction is available in 64-bit mode only.
It is an extension ofthe functionality provided by CMPXCHG8B that operates on 128-bits of data.7.3.1.4Stack Manipulation InstructionsThe PUSH, POP, PUSHA (push all registers), and POPA (pop all registers) instructionsmove data to and from the stack. The PUSH instruction decrements the stack pointer(contained in the ESP register), then copies the source operand to the top of stack(see Figure 7-1).
It operates on memory operands, immediate operands, andregister operands (including segment registers). The PUSH instruction is commonlyused to place parameters on the stack before calling a procedure. It can also be usedto reserve space on the stack for temporary variables.Vol. 1 7-7PROGRAMMING WITH GENERAL-PURPOSE INSTRUCTIONSStackBefore Pushing DoublewordStackGrowth31After Pushing Doubleword310nn−4n−80ESPDoubleword ValueESPFigure 7-1. Operation of the PUSH InstructionThe PUSHA instruction saves the contents of the eight general-purpose registers onthe stack (see Figure 7-2). This instruction simplifies procedure calls by reducing thenumber of instructions required to save the contents of the general-purpose registers.
The registers are pushed on the stack in the following order: EAX, ECX, EDX,EBX, the initial value of ESP before EAX was pushed, EBP, ESI, and EDI.StackStackGrowthnn-4n-8n - 12n - 16n - 20n - 24n - 28n - 32n - 36Before Pushing Registers310After Pushing Registers310ESPEAXECXEDXEBXOld ESPEBPESIEDIESPFigure 7-2.
Operation of the PUSHA InstructionThe POP instruction copies the word or doubleword at the current top of stack (indicated by the ESP register) to the location specified with the destination operand. Itthen increments the ESP register to point to the new top of stack (see Figure 7-3).The destination operand may specify a general-purpose register, a segment register,or a memory location.7-8 Vol. 1PROGRAMMING WITH GENERAL-PURPOSE INSTRUCTIONSStackBefore Popping DoublewordStackGrowth31nn-4n-8After Popping Doubleword0310ESPDoubleword ValueESPFigure 7-3. Operation of the POP InstructionThe POPA instruction reverses the effect of the PUSHA instruction.
It pops the topeight words or doublewords from the top of the stack into the general-purpose registers, except for the ESP register (see Figure 7-4). If the operand-size attribute is 32,the doublewords on the stack are transferred to the registers in the following order:EDI, ESI, EBP, ignore doubleword, EBX, EDX, ECX, and EAX. The ESP register isrestored by the action of popping the stack. If the operand-size attribute is 16, thewords on the stack are transferred to the registers in the following order: DI, SI, BP,ignore word, BX, DX, CX, and AX.StackStackGrowthBefore Popping Registers031nn-4n-8n - 12n - 16n - 20n - 24n - 28n - 32n - 36After Popping Registers031ESPEAXECXEDXEBXIgnoredEBPESIEDIESPFigure 7-4.
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