Volume 1 Basic Architecture (794100), страница 42
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Inaddition, procedure B can pass parameters to procedure C either on the stack orthrough variables global to both procedures (that is, variables in the scope of bothprocedures).Old EBPMain’s EBPMain’s EBPMain’s EBPProcedure A’s EBPProcedure A’s EBPDisplayEBPMain’s EBPProcedure A’s EBPProcedure B’s EBPDynamicStorageESPFigure 6-9. Stack Frame After Entering Procedure B6-24 Vol. 2PROCEDURE CALLS, INTERRUPTS, AND EXCEPTIONSOld EBPMain’s EBPMain’s EBPMain’s EBPProcedure A’s EBPProcedure A’s EBPMain’s EBPProcedure A’s EBPProcedure B’s EBPProcedure B’s EBPDisplayEBPMain’s EBPProcedure A’s EBPProcedure C’s EBPDynamicStorageESPFigure 6-10. Stack Frame After Entering Procedure C6.5.2LEAVE InstructionThe LEAVE instruction, which does not have any operands, reverses the action of theprevious ENTER instruction. The LEAVE instruction copies the contents of the EBPregister into the ESP register to release all stack space allocated to the procedure.Then it restores the old value of the EBP register from the stack.
This simultaneouslyrestores the ESP register to its original value. A subsequent RET instruction then canremove any arguments and the return address pushed on the stack by the callingprogram for use by the procedure.Vol. 2 6-25PROCEDURE CALLS, INTERRUPTS, AND EXCEPTIONS6-26 Vol. 2CHAPTER 7PROGRAMMING WITHGENERAL-PURPOSE INSTRUCTIONSGeneral-purpose (GP) instructions are a subset of the IA-32 instructions that represent the fundamental instruction set for the Intel IA-32 processors.
These instructions were introduced into the IA-32 architecture with the first IA-32 processors (theIntel 8086 and 8088). Additional instructions were added to the general-purposeinstruction set in subsequent families of IA-32 processors (the Intel 286, Intel386,Intel486, Pentium, Pentium Pro, and Pentium II processors).Intel 64 architecture further extends the capability of most general-purpose instructions so that they are able to handle 64-bit data in 64-bit mode. A small number ofgeneral-purpose instructions (still supported in non-64-bit modes) are not supportedin 64-bit mode.General-purpose instructions perform basic data movement, memory addressing,arithmetic and logical, program flow control, input/output, and string operations on aset of integer, pointer, and BCD data types.
This chapter provides an overview of thegeneral-purpose instructions. See Intel® 64 and IA-32 Architectures SoftwareDeveloper’s Manual, Volumes 3A & 3B, for detailed descriptions of individual instructions.7.1PROGRAMMING ENVIRONMENT FOR GPINSTRUCTIONSThe programming environment for the general-purpose instructions consists of theset of registers and address space.
The environment includes the following items:•General-purpose registers — Eight 32-bit general-purpose registers (seeSection 3.4.1, “General-Purpose Registers”) are used in non-64-bit modes toaddress operands in memory. These registers are referenced by the names EAX,EBX, ECX, EDX, EBP, ESI EDI, and ESP.•Segment registers — The six 16-bit segment registers contain segmentpointers for use in accessing memory (see Section 3.4.2, “Segment Registers”).These registers are referenced by the names CS, DS, SS, ES, FS, and GS.•EFLAGS register — This 32-bit register (see Section 3.4.3, “EFLAGS Register”)is used to provide status and control for basic arithmetic, compare, and systemoperations.•EIP register — This 32-bit register contains the current instruction pointer (seeSection 3.4.3, “EFLAGS Register”).General-purpose instructions operate on the following data types.
The width of validdata types is dependent on processor mode (see Chapter 4):Vol. 1 7-1PROGRAMMING WITH GENERAL-PURPOSE INSTRUCTIONS•••••Bytes, words, doublewordsSigned and unsigned byte, word, doubleword integersNear and far pointersBit fieldsBCD integers7.2PROGRAMMING ENVIRONMENT FOR GPINSTRUCTIONS IN 64-BIT MODEThe programming environment for the general-purpose instructions in 64-bit mode issimilar to that described in Section 7.1.•General-purpose registers — In 64-bit mode, sixteen general-purposeregisters available. These include the eight GPRs described in Section 7.1 andeight new GPRs (R8D-R15D).
R8D-R15D are available by using a REX prefix. Allsixteen GPRs can be promoted to 64 bits. The 64-bit registers are referenced asRAX, RBX, RCX, RDX, RBP, RSI, RDI, RSP and R8-R15 (see Section 3.4.1.1,“General-Purpose Registers in 64-Bit Mode”). Promotion to 64-bit operandrequires REX prefix encodings.•Segment registers — In 64-bit mode, segmentation is available but it is set upuniquely (see Section 3.4.2.1, “Segment Registers in 64-Bit Mode”).•Flags and Status register — When the processor is running in 64-bit mode,EFLAGS becomes the 64-bit RFLAGS register (see Section 3.4.3, “EFLAGSRegister”).•Instruction Pointer register — In 64-bit mode, the EIP register becomes the64-bit RIP register (see Section 3.5.1, “Instruction Pointer in 64-Bit Mode”).General-purpose instructions operate on the following data types in 64-bit mode. Thewidth of valid data types is dependent on default operand size, address size, or aprefix that overrides the default size:••••Bytes, words, doublewords, quadwordsSigned and unsigned byte, word, doubleword, quadword integersNear and far pointersBit fieldsSee also:•Chapter 3, “Basic Execution Environment,” for more information about IA-32emodes.•Chapter 2, “Instruction Format,” in the Intel® 64 and IA-32 ArchitecturesSoftware Developer’s Manual, Volume 2A, for more detailed information aboutREX prefixes.7-2 Vol.
1PROGRAMMING WITH GENERAL-PURPOSE INSTRUCTIONS•Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volumes2A & 2B for a complete listing of all instructions. This information documents thebehavior of individual instructions in the 64-bit mode context.7.3SUMMARY OF GP INSTRUCTIONSGeneral purpose instructions are divided into the following subgroups:•••••••••••••Data transferBinary arithmeticDecimal arithmeticLogicalShift and rotateBit and byteControl transferStringI/OEnter and LeaveFlag controlSegment registerMiscellaneousEach sub-group of general-purpose instructions is discussed in the context of non64-bit mode operation first. Changes in 64-bit mode beyond those affected by theuse of the REX prefixes are discussed in separate sub-sections within each subgroup.For a simple list of general-purpose instructions by subgroup, see Chapter 5.7.3.1Data Transfer InstructionsThe data transfer instructions move bytes, words, doublewords, or quadwords bothbetween memory and the processor’s registers and between registers.
For thepurpose of this discussion, these instructions are divided into subordinate subgroupsthat provide for:••••General data movementExchangeStack manipulationType conversionVol. 1 7-3PROGRAMMING WITH GENERAL-PURPOSE INSTRUCTIONS7.3.1.1General Data Movement InstructionsMove instructions — The MOV (move) and CMOVcc (conditional move) instructionstransfer data between memory and registers or between registers.The MOV instruction performs basic load data and store data operations betweenmemory and the processor’s registers and data movement operations between registers. It handles data transfers along the paths listed in Table 7-1. (See “MOV—Moveto/from Control Registers” and “MOV—Move to/from Debug Registers” in Chapter 3,“Instruction Set Reference, A-M,” of the Intel® 64 and IA-32 Architectures SoftwareDeveloper’s Manual, Volume 2A, for information on moving data to and from thecontrol and debug registers.)The MOV instruction cannot move data from one memory location to another or fromone segment register to another segment register.
Memory-to-memory moves areperformed with the MOVS (string move) instruction (see Section 7.3.9, “String Operations”).Conditional move instructions — The CMOVcc instructions are a group of instructions that check the state of the status flags in the EFLAGS register and perform amove operation if the flags are in a specified state.
These instructions can be used tomove a 16-bit or 32-bit value from memory to a general-purpose register or fromone general-purpose register to another. The flag state being tested is specified witha condition code (cc) associated with the instruction. If the condition is not satisfied,a move is not performed and execution continues with the instruction following theCMOVcc instruction.Table 7-1. Move Instruction OperationsType of Data MovementFrom memory to a registerSource → DestinationMemory location → General-purpose registerMemory location → Segment registerFrom a register to memoryGeneral-purpose register → Memory locationSegment register → Memory locationBetween registersGeneral-purpose register → General-purpose registerGeneral-purpose register → Segment registerSegment register → General-purpose registerGeneral-purpose register → Control registerControl register → General-purpose registerGeneral-purpose register → Debug registerDebug register → General-purpose registerImmediate data to a registerImmediate → General-purpose registerImmediate data to memoryImmediate → Memory location7-4 Vol.
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