Volume 1 Basic Architecture (794100), страница 37
Текст из файла (страница 37)
For example, inmultitasking systems, each task can be given its own stack. The number of stacks ina system is limited by the maximum number of segments and the available physicalmemory.Vol. 2 6-1PROCEDURE CALLS, INTERRUPTS, AND EXCEPTIONSWhen a system sets up many stacks, only one stack—the current stack—is available at a time. The current stack is the one contained in the segment referenced bythe SS register.Stack SegmentBottom of Stack(Initial ESP Value)Local Variablesfor CallingProcedureThe Stack Can Be16 or 32 Bits WideParametersPassed toCalledProcedureThe EBP register istypically set to pointto the returninstruction pointer.Frame BoundaryReturn InstructionPointerEBP RegisterESP RegisterTop of StackPushes Move theTop Of Stack toLower AddressesPops Move theTop Of Stack toHigher AddressesFigure 6-1. Stack StructureThe processor references the SS register automatically for all stack operations.
Forexample, when the ESP register is used as a memory address, it automatically pointsto an address in the current stack. Also, the CALL, RET, PUSH, POP, ENTER, andLEAVE instructions all perform operations on the current stack.6.2.1Setting Up a StackTo set a stack and establish it as the current stack, the program or operatingsystem/executive must do the following:1. Establish a stack segment.2. Load the segment selector for the stack segment into the SS register using aMOV, POP, or LSS instruction.6-2 Vol. 2PROCEDURE CALLS, INTERRUPTS, AND EXCEPTIONS3. Load the stack pointer for the stack into the ESP register using a MOV, POP, orLSS instruction. The LSS instruction can be used to load the SS and ESP registersin one operation.See “Segment Descriptors” in of the Intel® 64 and IA-32 Architectures SoftwareDeveloper’s Manual, Volume 3A, for information on how to set up a segmentdescriptor and segment limits for a stack segment.6.2.2Stack AlignmentThe stack pointer for a stack segment should be aligned on 16-bit (word) or 32-bit(double-word) boundaries, depending on the width of the stack segment.
The D flagin the segment descriptor for the current code segment sets the stack-segment width(see “Segment Descriptors” in Chapter 3, “Protected-Mode Memory Management,” ofthe Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 3A).The PUSH and POP instructions use the D flag to determine how much to decrementor increment the stack pointer on a push or pop operation, respectively. When thestack width is 16 bits, the stack pointer is incremented or decremented in 16-bitincrements; when the width is 32 bits, the stack pointer is incremented or decremented in 32-bit increments.
Pushing a 16-bit value onto a 32-bit wide stack canresult in stack misaligned (that is, the stack pointer is not aligned on a doublewordboundary). One exception to this rule is when the contents of a segment register (a16-bit segment selector) are pushed onto a 32-bit wide stack. Here, the processorautomatically aligns the stack pointer to the next 32-bit boundary.The processor does not check stack pointer alignment. It is the responsibility of theprograms, tasks, and system procedures running on the processor to maintainproper alignment of stack pointers.
Misaligning a stack pointer can cause seriousperformance degradation and in some instances program failures.6.2.3Address-Size Attributes for Stack AccessesInstructions that use the stack implicitly (such as the PUSH and POP instructions)have two address-size attributes each of either 16 or 32 bits. This is because theyalways have the implicit address of the top of the stack, and they may also have anexplicit memory address (for example, PUSH Array1[EBX]).
The attribute of theexplicit address is determined by the D flag of the current code segment and thepresence or absence of the 67H address-size prefix.The address-size attribute of the top of the stack determines whether SP or ESP isused for the stack access. Stack operations with an address-size attribute of 16 usethe 16-bit SP stack pointer register and can use a maximum stack address of FFFFH;stack operations with an address-size attribute of 32 bits use the 32-bit ESP registerand can use a maximum address of FFFFFFFFH. The default address-size attribute fordata segments used as stacks is controlled by the B flag of the segment’s descriptor.When this flag is clear, the default address-size attribute is 16; when the flag is set,the address-size attribute is 32.Vol.
2 6-3PROCEDURE CALLS, INTERRUPTS, AND EXCEPTIONS6.2.4Procedure Linking InformationThe processor provides two pointers for linking of procedures: the stack-frame basepointer and the return instruction pointer. When used in conjunction with a standardsoftware procedure-call technique, these pointers permit reliable and coherentlinking of procedures.6.2.4.1Stack-Frame Base PointerThe stack is typically divided into frames.
Each stack frame can then contain localvariables, parameters to be passed to another procedure, and procedure linkinginformation. The stack-frame base pointer (contained in the EBP register) identifies afixed reference point within the stack frame for the called procedure. To use thestack-frame base pointer, the called procedure typically copies the contents of theESP register into the EBP register prior to pushing any local variables on the stack.The stack-frame base pointer then permits easy access to data structures passed onthe stack, to the return instruction pointer, and to local variables added to the stackby the called procedure.Like the ESP register, the EBP register automatically points to an address in thecurrent stack segment (that is, the segment specified by the current contents of theSS register).6.2.4.2Return Instruction PointerPrior to branching to the first instruction of the called procedure, the CALL instructionpushes the address in the EIP register onto the current stack.
This address is thencalled the return-instruction pointer and it points to the instruction where executionof the calling procedure should resume following a return from the called procedure.Upon returning from a called procedure, the RET instruction pops the return-instruction pointer from the stack back into the EIP register. Execution of the calling procedure then resumes.The processor does not keep track of the location of the return-instruction pointer. Itis thus up to the programmer to insure that stack pointer is pointing to the returninstruction pointer on the stack, prior to issuing a RET instruction. A common way toreset the stack pointer to the point to the return-instruction pointer is to move thecontents of the EBP register into the ESP register. If the EBP register is loaded withthe stack pointer immediately following a procedure call, it should point to the returninstruction pointer on the stack.The processor does not require that the return instruction pointer point back to thecalling procedure.
Prior to executing the RET instruction, the return instructionpointer can be manipulated in software to point to any address in the current codesegment (near return) or another code segment (far return). Performing such anoperation, however, should be undertaken very cautiously, using only well definedcode entry points.6-4 Vol.
2PROCEDURE CALLS, INTERRUPTS, AND EXCEPTIONS6.2.5Stack Behavior in 64-Bit ModeIn 64-bit mode, address calculations that reference SS segments are treated as if thesegment base is zero. Fields (base, limit, and attribute) in segment descriptor registers are ignored. SS DPL is modified such that it is always equal to CPL. This will betrue even if it is the only field in the SS descriptor that is modified.Registers E(SP), E(IP) and E(BP) are promoted to 64-bits and are re-named RSP, RIP,and RBP respectively. Some forms of segment load instructions are invalid (forexample, LDS, POP ES).PUSH/POP instructions increment/decrement the stack using a 64-bit width.
Whenthe contents of a segment register is pushed onto 64-bit stack, the pointer is automatically aligned to 64 bits (as with a stack that has a 32-bit width).6.3CALLING PROCEDURES USING CALL AND RETThe CALL instruction allows control transfers to procedures within the current codesegment (near call) and in a different code segment (far call). Near calls usuallyprovide access to local procedures within the currently running program or task. Farcalls are usually used to access operating system procedures or procedures in adifferent task. See “CALL—Call Procedure” in Chapter 3, “Instruction Set Reference,A-M,” of the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume2A, for a detailed description of the CALL instruction.The RET instruction also allows near and far returns to match the near and farversions of the CALL instruction.
In addition, the RET instruction allows a program toincrement the stack pointer on a return to release parameters from the stack. Thenumber of bytes released from the stack is determined by an optional argument (n)to the RET instruction. See “RET—Return from Procedure” in Chapter 4, “InstructionSet Reference, N-Z,” of the Intel® 64 and IA-32 Architectures Software Developer’sManual, Volume 2B, for a detailed description of the RET instruction.6.3.1Near CALL and RET OperationWhen executing a near call, the processor does the following (see Figure 6-2):1.
![](https://s.studizba.com/z.php?f=/templates/si/i/noavatar.png&w=100&h=100&t=1"){kind=avatar}
