Volume 1 Basic Architecture (794100), страница 34
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1INSTRUCTION SET SUMMARY5.5.1SSE SIMD Single-Precision Floating-Point InstructionsThese instructions operate on packed and scalar single-precision floating-pointvalues located in XMM registers and/or memory. This subgroup is further divided intothe following subordinate subgroups: data transfer, packed arithmetic, comparison,logical, shuffle and unpack, and conversion instructions.5.5.1.1SSE Data Transfer InstructionsSSE data transfer instructions move packed and scalar single-precision floating-pointoperands between XMM registers and between XMM registers and memory.MOVAPSMove four aligned packed single-precision floating-point valuesbetween XMM registers or between and XMM register andmemoryMOVUPSMove four unaligned packed single-precision floating-pointvalues between XMM registers or between and XMM register andmemoryMOVHPSMove two packed single-precision floating-point values to anfrom the high quadword of an XMM register and memoryMOVHLPSMove two packed single-precision floating-point values from thehigh quadword of an XMM register to the low quadword ofanother XMM registerMOVLPSMove two packed single-precision floating-point values to anfrom the low quadword of an XMM register and memoryMOVLHPSMove two packed single-precision floating-point values from thelow quadword of an XMM register to the high quadword ofanother XMM registerMOVMSKPSExtract sign mask from four packed single-precision floatingpoint valuesMOVSSMove scalar single-precision floating-point value between XMMregisters or between an XMM register and memory5.5.1.2SSE Packed Arithmetic InstructionsSSE packed arithmetic instructions perform packed and scalar arithmetic operationson packed and scalar single-precision floating-point operands.ADDPSAdd packed single-precision floating-point valuesADDSSAdd scalar single-precision floating-point valuesSUBPSSubtract packed single-precision floating-point valuesSUBSSSubtract scalar single-precision floating-point valuesMULPSMultiply packed single-precision floating-point valuesMULSSMultiply scalar single-precision floating-point valuesDIVPSDivide packed single-precision floating-point valuesVol.
1 5-17INSTRUCTION SET SUMMARYDIVSSDivide scalar single-precision floating-point valuesRCPPSCompute reciprocals of packed single-precision floating-pointvaluesRCPSSCompute reciprocal of scalar single-precision floating-pointvaluesSQRTPSCompute square roots of packed single-precision floating-pointvaluesSQRTSSCompute square root of scalar single-precision floating-pointvaluesRSQRTPSCompute reciprocals of square roots of packed single-precisionfloating-point valuesRSQRTSSCompute reciprocal of square root of scalar single-precisionfloating-point valuesMAXPSReturn maximum packed single-precision floating-point valuesMAXSSReturn maximum scalar single-precision floating-point valuesMINPSReturn minimum packed single-precision floating-point valuesMINSSReturn minimum scalar single-precision floating-point values5.5.1.3SSE Comparison InstructionsSSE compare instructions compare packed and scalar single-precision floating-pointoperands.CMPPSCompare packed single-precision floating-point valuesCMPSSCompare scalar single-precision floating-point valuesCOMISSPerform ordered comparison of scalar single-precision floatingpoint values and set flags in EFLAGS registerUCOMISSPerform unordered comparison of scalar single-precisionfloating-point values and set flags in EFLAGS register5.5.1.4SSE Logical InstructionsSSE logical instructions perform bitwise AND, AND NOT, OR, and XOR operations onpacked single-precision floating-point operands.ANDPSPerform bitwise logical AND of packed single-precision floatingpoint valuesANDNPSPerform bitwise logical AND NOT of packed single-precisionfloating-point valuesORPSPerform bitwise logical OR of packed single-precision floatingpoint valuesXORPSPerform bitwise logical XOR of packed single-precision floatingpoint values5-18 Vol.
1INSTRUCTION SET SUMMARY5.5.1.5SSE Shuffle and Unpack InstructionsSSE shuffle and unpack instructions shuffle or interleave single-precision floatingpoint values in packed single-precision floating-point operands.SHUFPSShuffles values in packed single-precision floating-pointoperandsUNPCKHPSUnpacks and interleaves the two high-order values from twosingle-precision floating-point operandsUNPCKLPSUnpacks and interleaves the two low-order values from twosingle-precision floating-point operands5.5.1.6SSE Conversion InstructionsSSE conversion instructions convert packed and individual doubleword integers intopacked and scalar single-precision floating-point values and vice versa.CVTPI2PSConvert packed doubleword integers to packed single-precisionfloating-point valuesCVTSI2SSConvert doubleword integer to scalar single-precision floatingpoint valueCVTPS2PIConvert packed single-precision floating-point values to packeddoubleword integersCVTTPS2PIConvert with truncation packed single-precision floating-pointvalues to packed doubleword integersCVTSS2SIConvert a scalar single-precision floating-point value to adoubleword integerCVTTSS2SIConvert with truncation a scalar single-precision floating-pointvalue to a scalar doubleword integer5.5.2SSE MXCSR State Management InstructionsMXCSR state management instructions allow saving and restoring the state of theMXCSR control and status register.LDMXCSRLoad MXCSR registerSTMXCSRSave MXCSR register state5.5.3SSE 64-Bit SIMD Integer InstructionsThese SSE 64-bit SIMD integer instructions perform additional operations on packedbytes, words, or doublewords contained in MMX registers.
They represent enhancements to the MMX instruction set described in Section 5.4, “MMX™ Instructions.”PAVGBCompute average of packed unsigned byte integersPAVGWCompute average of packed unsigned word integersVol. 1 5-19INSTRUCTION SET SUMMARYPEXTRWExtract wordPINSRWInsert wordPMAXUBMaximum of packed unsigned byte integersPMAXSWMaximum of packed signed word integersPMINUBMinimum of packed unsigned byte integersPMINSWMinimum of packed signed word integersPMOVMSKBMove byte maskPMULHUWMultiply packed unsigned integers and store high resultPSADBWCompute sum of absolute differencesPSHUFWShuffle packed integer word in MMX register5.5.4SSE Cacheability Control, Prefetch, and Instruction OrderingInstructionsThe cacheability control instructions provide control over the caching of nontemporal data when storing data from the MMX and XMM registers to memory.
ThePREFETCHh allows data to be prefetched to a selected cache level. The SFENCEinstruction controls instruction ordering on store operations.MASKMOVQNon-temporal store of selected bytes from an MMX register intomemoryMOVNTQNon-temporal store of quadword from an MMX register intomemoryMOVNTPSNon-temporal store of four packed single-precision floatingpoint values from an XMM register into memoryPREFETCHhLoad 32 or more of bytes from memory to a selected level of theprocessor’s cache hierarchySFENCESerializes store operations5.6SSE2 INSTRUCTIONSSSE2 extensions represent an extension of the SIMD execution model introducedwith MMX technology and the SSE extensions. SSE2 instructions operate on packeddouble-precision floating-point operands and on packed byte, word, doubleword, andquadword operands located in the XMM registers.
For more detail on these instructions, see Chapter 11, “Programming with Streaming SIMD Extensions 2 (SSE2).”SSE2 instructions can only be executed on Intel 64 and IA-32 processors thatsupport the SSE2 extensions. Support for these instructions can be detected with theCPUID instruction. See the description of the CPUID instruction in Chapter 3,“Instruction Set Reference, A-M,” of the Intel® 64 and IA-32 Architectures SoftwareDeveloper’s Manual, Volume 2A.5-20 Vol. 1INSTRUCTION SET SUMMARYThese instructions are divided into four subgroups (note that the first subgroup isfurther divided into subordinate subgroups):••••Packed and scalar double-precision floating-point instructionsPacked single-precision floating-point conversion instructions128-bit SIMD integer instructionsCacheability-control and instruction ordering instructionsThe following sections give an overview of each subgroup.5.6.1SSE2 Packed and Scalar Double-Precision Floating-PointInstructionsSSE2 packed and scalar double-precision floating-point instructions are divided intothe following subordinate subgroups: data movement, arithmetic, comparison,conversion, logical, and shuffle operations on double-precision floating-point operands.
These are introduced in the sections that follow.5.6.1.1SSE2 Data Movement InstructionsSSE2 data movement instructions move double-precision floating-point databetween XMM registers and between XMM registers and memory.MOVAPDMove two aligned packed double-precision floating-point valuesbetween XMM registers or between and XMM register andmemoryMOVUPDMove two unaligned packed double-precision floating-pointvalues between XMM registers or between and XMM register andmemoryMOVHPDMove high packed double-precision floating-point value to anfrom the high quadword of an XMM register and memoryMOVLPDMove low packed single-precision floating-point value to an fromthe low quadword of an XMM register and memoryMOVMSKPDExtract sign mask from two packed double-precision floatingpoint valuesMOVSDMove scalar double-precision floating-point value between XMMregisters or between an XMM register and memory5.6.1.2SSE2 Packed Arithmetic InstructionsThe arithmetic instructions perform addition, subtraction, multiply, divide, squareroot, and maximum/minimum operations on packed and scalar double-precisionfloating-point operands.ADDPDAdd packed double-precision floating-point valuesVol.
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