Volume 1 Basic Architecture (794100), страница 29
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When anSNaN is converted to a QNaN, the conversion is handled by setting the mostsignificant fraction bit of the SNaN to 1. Also, when one of the source operands isan SNaN, the floating-point invalid-operation exception flag it set. Note that forsome combinations of source operands, the result is different for x87 FPUoperations and for SSE/SSE2/SSE3 operations.•When neither of the source operands is a NaN, but the operation generates afloating-point invalid-operation exception (see Tables 8-10 and 11-1), the resultis commonly an SNaN source operand converted to a QNaN or the QNaN floatingpoint indefinite value.Any exceptions to the behavior described in Table 4-7 are described in Section8.5.1.2, “Invalid Arithmetic Operand Exception (#IA),” and Section 11.5.2.1, “InvalidOperation Exception (#I).”4-20 Vol.
1DATA TYPESTable 4-7. Rules for Handling NaNsSource OperandsResult1SNaN and QNaNx87 FPU — QNaN source operand.SSE/SSE2/SSE3 — First operand (if this operand isan SNaN, it is converted to a QNaN)Two SNaNsx87 FPU—SNaN source operand with the largersignificand, converted into a QNaNSSE/SSE2/SSE3 — First operand converted to aQNaNTwo QNaNsx87 FPU — QNaN source operand with the largersignificandSSE/SSE2/SSE3 — First operandSNaN and a floating-point valueSNaN source operand, converted into a QNaNQNaN and a floating-point valueQNaN source operandSNaN (for instructions that take only oneoperand)SNaN source operand, converted into a QNaNQNaN (for instructions that take only oneoperand)QNaN source operandNOTE:1.
For SSE/SSE2/SSE3 instructions, the first operand is generally a source operand that becomesthe destination operand. Within the Result column, the x87 FPU notation also applies to theFISTTP instruction in SSE3; the SSE3 notation applies to the SIMD floating-point instructions.4.8.3.6Using SNaNs and QNaNs in ApplicationsExcept for the rules given at the beginning of Section 4.8.3.4, “NaNs,” for encodingSNaNs and QNaNs, software is free to use the bits in the significand of a NaN for anypurpose. Both SNaNs and QNaNs can be encoded to carry and store data, such asdiagnostic information.By unmasking the invalid operation exception, the programmer can use signalingNaNs to trap to the exception handler.
The generality of this approach and the largenumber of NaN values that are available provide the sophisticated programmer witha tool that can be applied to a variety of special situations.For example, a compiler can use signaling NaNs as references to uninitialized (real)array elements. The compiler can preinitialize each array element with a signalingNaN whose significand contained the index (relative position) of the element. Then,if an application program attempts to access an element that it had not initialized, itcan use the NaN placed there by the compiler. If the invalid operation exception isunmasked, an interrupt will occur, and the exception handler will be invoked.
Theexception handler can determine which element has been accessed, since theVol. 1 4-21DATA TYPESoperand address field of the exception pointer will point to the NaN, and the NaN willcontain the index number of the array element.Quiet NaNs are often used to speed up debugging. In its early testing phase, aprogram often contains multiple errors. An exception handler can be written to savediagnostic information in memory whenever it was invoked. After storing the diagnostic data, it can supply a quiet NaN as the result of the erroneous instruction, andthat NaN can point to its associated diagnostic area in memory. The program willthen continue, creating a different NaN for each error. When the program ends, theNaN results can be used to access the diagnostic data saved at the time the errorsoccurred.
Many errors can thus be diagnosed and corrected in one test run.In embedded applications that use computed results in further computations, anundetected QNaN can invalidate all subsequent results. Such applications shouldtherefore periodically check for QNaNs and provide a recovery mechanism to be usedif a QNaN result is detected.4.8.3.7QNaN Floating-Point IndefiniteFor the floating-point data type encodings (single-precision, double-precision, anddouble-extended-precision), one unique encoding (a QNaN) is reserved for representing the special value QNaN floating-point indefinite.
The x87 FPU and theSSE/SSE2/SSE3 extensions return these indefinite values as responses to somemasked floating-point exceptions. Table 4-3 shows the encoding used for the QNaNfloating-point indefinite.4.8.4RoundingWhen performing floating-point operations, the processor produces an infinitelyprecise floating-point result in the destination format (single-precision, double-precision, or double extended-precision floating-point) whenever possible. However,because only a subset of the numbers in the real number continuum can be represented in IEEE Standard 754 floating-point formats, it is often the case that an infinitely precise result cannot be encoded exactly in the format of the destinationoperand.For example, the following value (a) has a 24-bit fraction.
The least-significant bit ofthis fraction (the underlined bit) cannot be encoded exactly in the single-precisionformat (which has only a 23-bit fraction):(a) 1.0001 0000 1000 0011 1001 0111E2 101To round this result (a), the processor first selects two representable fractions b andc that most closely bracket a in value (b < a < c).(b) 1.0001 0000 1000 0011 1001 011E2 101(c) 1.0001 0000 1000 0011 1001 100E2 1014-22 Vol. 1DATA TYPESThe processor then sets the result to b or to c according to the selected roundingmode.
Rounding introduces an error in a result that is less than one unit in the lastplace (the least significant bit position of the floating-point value) to which the resultis rounded.The IEEE Standard 754 defines four rounding modes (see Table 4-8): round tonearest, round up, round down, and round toward zero. The default rounding mode(for the Intel 64 and IA-32 architectures) is round to nearest. This mode provides themost accurate and statistically unbiased estimate of the true result and is suitable formost applications.Table 4-8. Rounding Modes and Encoding of Rounding Control (RC) FieldRoundingModeRC FieldSettingDescriptionRound tonearest (even)00BRounded result is the closest to the infinitely precise result.
If twovalues are equally close, the result is the even value (that is, theone with the least-significant bit of zero). DefaultRound down(toward −∞)01BRounded result is closest to but no greater than the infinitelyprecise result.Round up(toward +∞)10BRounded result is closest to but no less than the infinitely preciseresult.Round toward 11Bzero (Truncate)Rounded result is closest to but no greater in absolute value thanthe infinitely precise result.The round up and round down modes are termed directed rounding and can beused to implement interval arithmetic. Interval arithmetic is used to determine upperand lower bounds for the true result of a multistep computation, when the intermediate results of the computation are subject to rounding.The round toward zero mode (sometimes called the “chop” mode) is commonly usedwhen performing integer arithmetic with the x87 FPU.The rounded result is called the inexact result.
When the processor produces aninexact result, the floating-point precision (inexact) flag (PE) is set (see Section4.9.1.6, “Inexact-Result (Precision) Exception (#P)”).The rounding modes have no effect on comparison operations, operations thatproduce exact results, or operations that produce NaN results.4.8.4.1Rounding Control (RC) FieldsIn the Intel 64 and IA-32 architectures, the rounding mode is controlled by a 2-bitrounding-control (RC) field (Table 4-8 shows the encoding of this field).
The RC fieldis implemented in two different locations:•x87 FPU control register (bits 10 and 11)Vol. 1 4-23DATA TYPES•The MXCSR register (bits 13 and 14)Although these two RC fields perform the same function, they control rounding fordifferent execution environments within the processor. The RC field in the x87 FPUcontrol register controls rounding for computations performed with the x87 FPUinstructions; the RC field in the MXCSR register controls rounding for SIMD floatingpoint computations performed with the SSE/SSE2 instructions.4.8.4.2Truncation with SSE and SSE2 Conversion InstructionsThe following SSE/SSE2 instructions automatically truncate the results of conversions from floating-point values to integers when the result it inexact: CVTTPD2DQ,CVTTPS2DQ, CVTTPD2PI, CVTTPS2PI, CVTTSD2SI, CVTTSS2SI.
Here, truncationmeans the round toward zero mode described in Table 4-8.4.9OVERVIEW OF FLOATING-POINT EXCEPTIONSThe following section provides an overview of floating-point exceptions and theirhandling in the IA-32 architecture. For information specific to the x87 FPU and to theSSE/SSE2/SSE3 extensions, refer to the following sections:••Section 8.4, “x87 FPU Floating-Point Exception Handling”Section 11.5, “SSE, SSE2, and SSE3 Exceptions”When operating on floating-point operands, the IA-32 architecture recognizes anddetects six classes of exception conditions:••••••Invalid operation (#I)Divide-by-zero (#Z)Denormalized operand (#D)Numeric overflow (#O)Numeric underflow (#U)Inexact result (precision) (#P)The nomenclature of “#” symbol followed by one or two letters (for example, #P) isused in this manual to indicate exception conditions.
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