Volume 1 Basic Architecture (794100), страница 30
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It is merely a short-hand formand is not related to assembler mnemonics.NOTEAll of the exceptions listed above except the denormal-operandexception (#D) are defined in IEEE Standard 754.The invalid-operation, divide-by-zero and denormal-operand exceptions are precomputation exceptions (that is, they are detected before any arithmetic operation4-24 Vol.
1DATA TYPESoccurs). The numeric-underflow, numeric-overflow and precision exceptions arepost-computation exceptions.Each of the six exception classes has a corresponding flag bit (IE, ZE, OE, UE, DE, orPE) and mask bit (IM, ZM, OM, UM, DM, or PM). When one or more floating-pointexception conditions are detected, the processor sets the appropriate flag bits, thentakes one of two possible courses of action, depending on the settings of the corresponding mask bits:•Mask bit set.
Handles the exception automatically, producing a predefined (andoften times usable) result, while allowing program execution to continue undisturbed.•Mask bit clear. Invokes a software exception handler to handle the exception.The masked (default) responses to exceptions have been chosen to deliver a reasonable result for each exception condition and are generally satisfactory for mostfloating-point applications. By masking or unmasking specific floating-point exceptions, programmers can delegate responsibility for most exceptions to the processorand reserve the most severe exception conditions for software exception handlers.Because the exception flags are “sticky,” they provide a cumulative record of theexceptions that have occurred since they were last cleared.
A programmer can thusmask all exceptions, run a calculation, and then inspect the exception flags to see ifany exceptions were detected during the calculation.In the IA-32 architecture, floating-point exception flag and mask bits are implemented in two different locations:•x87 FPU status word and control word. The flag bits are located at bits 0 through5 of the x87 FPU status word and the mask bits are located at bits 0 through 5 ofthe x87 FPU control word (see Figures 8-4 and 8-6).•MXCSR register. The flag bits are located at bits 0 through 5 of the MXCSRregister and the mask bits are located at bits 7 through 12 of the register (seeFigure 10-3).Although these two sets of flag and mask bits perform the same function, they reporton and control exceptions for different execution environments within the processor.The flag and mask bits in the x87 FPU status and control words control exceptionreporting and masking for computations performed with the x87 FPU instructions;the companion bits in the MXCSR register control exception reporting and maskingfor SIMD floating-point computations performed with the SSE/SSE2/SSE3 instructions.Note that when exceptions are masked, the processor may detect multiple exceptions in a single instruction, because it continues executing the instruction afterperforming its masked response.
For example, the processor can detect a denormalized operand, perform its masked response to this exception, and then detectnumeric underflow.See Section 4.9.2, “Floating-Point Exception Priority,” for a description of the rules forexception precedence when more than one floating-point exception condition isdetected for an instruction.Vol. 1 4-25DATA TYPES4.9.1Floating-Point Exception ConditionsThe following sections describe the various conditions that cause a floating-pointexception to be generated and the masked response of the processor when theseconditions are detected. The Intel® 64 and IA-32 Architectures Software Developer’sManual, Volumes 3A & 3B, list the floating-point exceptions that can be signaled foreach floating-point instruction.4.9.1.1Invalid Operation Exception (#I)The processor reports an invalid operation exception in response to one or moreinvalid arithmetic operands.
If the invalid operation exception is masked, theprocessor sets the IE flag and returns an indefinite value or a QNaN. This value overwrites the destination register specified by the instruction. If the invalid operationexception is not masked, the IE flag is set, a software exception handler is invoked,and the operands remain unaltered.See Section 4.8.3.6, “Using SNaNs and QNaNs in Applications,” for information aboutthe result returned when an exception is caused by an SNaN.The processor can detect a variety of invalid arithmetic operations that can be codedin a program. These operations generally indicate a programming error, such asdividing ∞ by ∞ .
See the following sections for information regarding the invalidoperation exception when detected while executing x87 FPU or SSE/SSE2/SSE3instructions:••x87 FPU; Section 8.5.1, “Invalid Operation Exception”SIMD floating-point exceptions; Section 11.5.2.1, “Invalid Operation Exception(#I)”4.9.1.2Denormal Operand Exception (#D)The processor reports the denormal-operand exception if an arithmetic instructionattempts to operate on a denormal operand (see Section 4.8.3.2, “Normalized andDenormalized Finite Numbers”). When the exception is masked, the processor setsthe DE flag and proceeds with the instruction. Operating on denormal numbers willproduce results at least as good as, and often better than, what can be obtainedwhen denormal numbers are flushed to zero. Programmers can mask this exceptionso that a computation may proceed, then analyze any loss of accuracy when the finalresult is delivered.When a denormal-operand exception is not masked, the DE flag is set, a softwareexception handler is invoked, and the operands remain unaltered.
When denormaloperands have reduced significance due to loss of low-order bits, it may be advisableto not operate on them. Precluding denormal operands from computations can beaccomplished by an exception handler that responds to unmasked denormaloperand exceptions.4-26 Vol. 1DATA TYPESSee the following sections for information regarding the denormal-operand exceptionwhen detected while executing x87 FPU or SSE/SSE2/SSE3 instructions:••x87 FPU; Section 8.5.2, “Denormal Operand Exception (#D)”SIMD floating-point exceptions; Section 11.5.2.2, “Denormal-Operand Exception(#D)”4.9.1.3Divide-By-Zero Exception (#Z)The processor reports the floating-point divide-by-zero exception whenever aninstruction attempts to divide a finite non-zero operand by 0. The masked responsefor the divide-by-zero exception is to set the ZE flag and return an infinity signed withthe exclusive OR of the sign of the operands.
If the divide-by-zero exception is notmasked, the ZE flag is set, a software exception handler is invoked, and the operandsremain unaltered.See the following sections for information regarding the divide-by-zero exceptionwhen detected while executing x87 FPU or SSE/SSE2 instructions:••x87 FPU; Section 8.5.3, “Divide-By-Zero Exception (#Z)”SIMD floating-point exceptions; Section 11.5.2.3, “Divide-By-Zero Exception(#Z)”4.9.1.4Numeric Overflow Exception (#O)The processor reports a floating-point numeric overflow exception whenever therounded result of an instruction exceeds the largest allowable finite value that will fitinto the destination operand. Table 4-9 shows the threshold range for numeric overflow for each of the floating-point formats; overflow occurs when a rounded resultfalls at or outside this threshold range.Vol. 1 4-27DATA TYPESTable 4-9. Numeric Overflow ThresholdsFloating-Point FormatOverflow ThresholdsSingle Precision| x | ≥ 1.0 ∗ 2128Double Precision| x | ≥ 1.0 ∗ 21024Double Extended Precision| x | ≥ 1.0 ∗ 216384When a numeric-overflow exception occurs and the exception is masked, theprocessor sets the OE flag and returns one of the values shown in Table 4-10,according to the current rounding mode.
See Section 4.8.4, “Rounding.”When numeric overflow occurs and the numeric-overflow exception is not masked,the OE flag is set, a software exception handler is invoked, and the source and destination operands either remain unchanged or a biased result is stored in the destination operand (depending whether the overflow exception was generated during anSSE/SSE2/SSE3 floating-point operation or an x87 FPU operation).Table 4-10. Masked Responses to Numeric OverflowRounding ModeSign of True ResultResultTo nearest++∞––∞+Largest finite positive number––∞++∞–Largest finite negative number+Largest finite positive number–Largest finite negative numberToward –∞Toward +∞Toward zeroSee the following sections for information regarding the numeric overflow exceptionwhen detected while executing x87 FPU instructions or while executingSSE/SSE2/SSE3 instructions:••x87 FPU; Section 8.5.4, “Numeric Overflow Exception (#O)”SIMD floating-point exceptions; Section 11.5.2.4, “Numeric Overflow Exception(#O)”4.9.1.5Numeric Underflow Exception (#U)The processor detects a floating-point numeric underflow condition whenever theresult of rounding with unbounded exponent (taking into account precision controlfor x87) is tiny; that is, less than the smallest possible normalized, finite value thatwill fit into the destination operand.
Table 4-11 shows the threshold range for4-28 Vol. 1DATA TYPESnumeric underflow for each of the floating-point formats (assuming normalizedresults); underflow occurs when a rounded result falls strictly within the thresholdrange. The ability to detect and handle underflow is provided to prevent a vary smallresult from propagating through a computation and causing another exception (suchas overflow during division) to be generated at a later time.Table 4-11. Numeric Underflow (Normalized) ThresholdsFloating-Point FormatUnderflow Thresholds*Single Precision| x | < 1.0 ∗ 2−126Double Precision| x | < 1.0 ∗ 2−1022Double Extended Precision| x | < 1.0 ∗ 2−16382* Where ‘x’ is the result rounded to destination precision with an unbounded exponent range.How the processor handles an underflow condition, depends on two related conditions:••creation of a tiny resultcreation of an inexact result; that is, a result that cannot be represented exactlyin the destination formatWhich of these events causes an underflow exception to be reported and how theprocessor responds to the exception condition depends on whether the underflowexception is masked:•Underflow exception masked — The underflow exception is reported (the UEflag is set) only when the result is both tiny and inexact.
The processor returns adenormalized result to the destination operand, regardless of inexactness.•Underflow exception not masked — The underflow exception is reportedwhen the result is tiny, regardless of inexactness. The processor leaves thesource and destination operands unaltered or stores a biased result in thedesignating operand (depending whether the underflow exception was generatedduring an SSE/SSE2/SSE3 floating-point operation or an x87 FPU operation) andinvokes a software exception handler.See the following sections for information regarding the numeric underflow exceptionwhen detected while executing x87 FPU instructions or while executingSSE/SSE2/SSE3 instructions:••x87 FPU; Section 8.5.5, “Numeric Underflow Exception (#U)”SIMD floating-point exceptions; Section 11.5.2.5, “Numeric Underflow Exception(#U)”4.9.1.6Inexact-Result (Precision) Exception (#P)The inexact-result exception (also called the precision exception) occurs if the resultof an operation is not exactly representable in the destination format.
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