Volume 1 Basic Architecture (794100), страница 25
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The mostcommon method of specifying a segment selector is to load it in a segment registerand then allow the processor to select the register implicitly, depending on the typeof operation being performed. The processor automatically chooses a segmentaccording to the rules given in Table 3-5.When storing data in memory or loading data from memory, the DS segment defaultcan be overridden to allow other segments to be accessed. Within an assembler, thesegment override is generally handled with a colon “:” operator. For example, thefollowing MOV instruction moves a value from register EAX into the segment pointedto by the ES register.
The offset into the segment is contained in the EBX register:MOV ES:[EBX], EAX;Table 3-5. Default Segment Selection RulesReferenceTypeRegisterUsedSegmentUsedDefault Selection RuleInstructionsCSCode SegmentAll instruction fetches.StackSSStack SegmentAll stack pushes and pops.Any memory reference which uses the ESP or EBPregister as a base register.Local DataDSData SegmentAll data references, except when relative to stack orstring destination.DestinationStringsESData Segmentpointed to withthe ES registerDestination of string instructions.At the machine level, a segment override is specified with a segment-override prefix,which is a byte placed at the beginning of an instruction.
The following defaultsegment selections cannot be overridden:••Instruction fetches must be made from the code segment.•Push and pop operations must always reference the SS segment.Destination strings in string instructions must be stored in the data segmentpointed to by the ES register.Vol. 1 3-29BASIC EXECUTION ENVIRONMENTSome instructions require a segment selector to be specified explicitly. In thesecases, the 16-bit segment selector can be located in a memory location or in a 16-bitregister.
For example, the following MOV instruction moves a segment selectorlocated in register BX into segment register DS:MOV DS, BXSegment selectors can also be specified explicitly as part of a 48-bit far pointer inmemory. Here, the first doubleword in memory contains the offset and the next wordcontains the segment selector.3.7.4.1Segmentation in 64-Bit ModeIn IA-32e mode, the effects of segmentation depend on whether the processor isrunning in compatibility mode or 64-bit mode. In compatibility mode, segmentationfunctions just as it does in legacy IA-32 mode, using the 16-bit or 32-bit protectedmode semantics described above.In 64-bit mode, segmentation is generally (but not completely) disabled, creating aflat 64-bit linear-address space.
The processor treats the segment base of CS, DS,ES, SS as zero, creating a linear address that is equal to the effective address. Theexceptions are the FS and GS segments, whose segment registers (which hold thesegment base) can be used as additional base registers in some linear address calculations.3.7.5Specifying an OffsetThe offset part of a memory address can be specified directly as a static value (calleda displacement) or through an address computation made up of one or more of thefollowing components:••••Displacement — An 8-, 16-, or 32-bit value.Base — The value in a general-purpose register.Index — The value in a general-purpose register.Scale factor — A value of 2, 4, or 8 that is multiplied by the index value.The offset which results from adding these components is called an effectiveaddress.
Each of these components can have either a positive or negative (2scomplement) value, with the exception of the scaling factor. Figure 3-11 shows allthe possible ways that these components can be combined to create an effectiveaddress in the selected segment.3-30 Vol. 1BASIC EXECUTION ENVIRONMENTBaseIndexEAXEBXECXEDXESPEBPESIEDIEAXEBXECXEDXEBPESIEDI+ScaleDisplacement1None2*48+8-bit16-bit32-bitOffset = Base + (Index * Scale) + DisplacementFigure 3-11. Offset (or Effective Address) ComputationThe uses of general-purpose registers as base or index components are restricted inthe following manner:••The ESP register cannot be used as an index register.When the ESP or EBP register is used as the base, the SS segment is the defaultsegment.
In all other cases, the DS segment is the default segment.The base, index, and displacement components can be used in any combination, andany of these components can be NULL. A scale factor may be used only when anindex also is used. Each possible combination is useful for data structures commonlyused by programmers in high-level languages and assembly language.The following addressing modes suggest uses for common combinations of addresscomponents.•Displacement ⎯ A displacement alone represents a direct (uncomputed) offsetto the operand.
Because the displacement is encoded in the instruction, this formof an address is sometimes called an absolute or static address. It is commonlyused to access a statically allocated scalar operand.•Base ⎯ A base alone represents an indirect offset to the operand. Since thevalue in the base register can change, it can be used for dynamic storage ofvariables and data structures.•Base + Displacement ⎯ A base register and a displacement can be usedtogether for two distinct purposes:— As an index into an array when the element size is not 2, 4, or 8 bytes—Thedisplacement component encodes the static offset to the beginning of thearray. The base register holds the results of a calculation to determine theoffset to a specific element within the array.— To access a field of a record: the base register holds the address of thebeginning of the record, while the displacement is a static offset to the field.An important special case of this combination is access to parameters in aprocedure activation record.
A procedure activation record is the stack frameVol. 1 3-31BASIC EXECUTION ENVIRONMENTcreated when a procedure is entered. Here, the EBP register is the best choice forthe base register, because it automatically selects the stack segment. This is acompact encoding for this common function.•(Index ∗ Scale) + Displacement ⎯ This address mode offers an efficient wayto index into a static array when the element size is 2, 4, or 8 bytes. Thedisplacement locates the beginning of the array, the index register holds thesubscript of the desired array element, and the processor automatically convertsthe subscript into an index by applying the scaling factor.•Base + Index + Displacement ⎯ Using two registers together supports eithera two-dimensional array (the displacement holds the address of the beginning ofthe array) or one of several instances of an array of records (the displacement isan offset to a field within the record).•Base + (Index ∗ Scale) + Displacement ⎯ Using all the addressingcomponents together allows efficient indexing of a two-dimensional array whenthe elements of the array are 2, 4, or 8 bytes in size.3.7.5.1Specifying an Offset in 64-Bit ModeThe offset part of a memory address in 64-bit mode can be specified directly as astatic value or through an address computation made up of one or more of thefollowing components:•••Displacement — An 8-bit, 16-bit, or 32-bit value.•Scale factor — A value of 2, 4, or 8 that is multiplied by the index value.Base — The value in a 32-bit (or 64-bit if REX.W is set) general-purpose register.Index — The value in a 32-bit (or 64-bit if REX.W is set) general-purposeregister.The base and index value can be specified in one of sixteen available general-purposeregisters in most cases.
See Chapter 2, “Instruction Format,” in the Intel® 64 andIA-32 Architectures Software Developer’s Manual, Volume 3A.The following unique combination of address components is also available.•RIP + Displacement ⎯ In 64-bit mode, RIP-relative addressing uses a signed32-bit displacement to calculate the effective address of the next instruction bysign-extend the 32-bit value and add to the 64-bit value in RIP.3.7.6Assembler and Compiler Addressing ModesAt the machine-code level, the selected combination of displacement, base register,index register, and scale factor is encoded in an instruction. All assemblers permit aprogrammer to use any of the allowable combinations of these addressing components to address operands.
High-level language compilers will select an appropriatecombination of these components based on the language construct a programmerdefines.3-32 Vol. 1BASIC EXECUTION ENVIRONMENT3.7.7I/O Port AddressingThe processor supports an I/O address space that contains up to 65,536 8-bit I/Oports. Ports that are 16-bit and 32-bit may also be defined in the I/O address space.An I/O port can be addressed with either an immediate operand or a value in the DXregister. See Chapter 13, “Input/Output,” for more information about I/O portaddressing.Vol. 1 3-33BASIC EXECUTION ENVIRONMENT3-34 Vol. 1CHAPTER 4DATA TYPESThis chapter introduces data types defined for the Intel 64 and IA-32 architectures.A section at the end of this chapter describes the real-number and floating-pointconcepts used in x87 FPU, SSE, SSE2, SSE3 and SSSE3 extensions.4.1FUNDAMENTAL DATA TYPESThe fundamental data types are bytes, words, doublewords, quadwords, and doublequadwords (see Figure 4-1).
A byte is eight bits, a word is 2 bytes (16 bits), adoubleword is 4 bytes (32 bits), a quadword is 8 bytes (64 bits), and a double quadword is 16 bytes (128 bits). A subset of the IA-32 architecture instructions operateson these fundamental data types without any additional operand typing.07ByteN15 8 7 0High LowByte Byte WordN+1 N31016 15High Word Low Word DoublewordN+263High Doubleword0QuadwordLow DoublewordN+4127N32 31N64 63High Quadword0Low QuadwordN+8DoubleQuadwordNFigure 4-1. Fundamental Data TypesThe quadword data type was introduced into the IA-32 architecture in the Intel486processor; the double quadword data type was introduced in the Pentium IIIprocessor with the SSE extensions.Figure 4-2 shows the byte order of each of the fundamental data types when referenced as operands in memory.
The low byte (bits 0 through 7) of each data typeoccupies the lowest address in memory and that address is also the address of theoperand.Vol. 1 4-1DATA TYPESWord at Address BHContains FE06HByte at Address 9HContains 1FHWord at Address 6HContains 230BHWord at Address 2HContains 74CBHWord at Address 1HContains CB31H12HEH7AHDHFEHCH06HBH36HAH1FH9HA4H8H23H7H0BH6H45H5H67H4H74H3HCBH2H31H1H12H0HDoubleword at Address AHContains 7AFE0636HQuadword at Address 6HContains7AFE06361FA4230BHDouble quadword at Address 0HContains127AFE06361FA4230B456774CB3112HFigure 4-2. Bytes, Words, Doublewords, Quadwords, and Double Quadwords inMemory4.1.1Alignment of Words, Doublewords, Quadwords, and DoubleQuadwordsWords, doublewords, and quadwords do not need to be aligned in memory on naturalboundaries.
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