Volume 1 Basic Architecture (794100), страница 24
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These attributes areselected with the D (default size) flag in the segment descriptor for the code segment(see Chapter 3, “Protected-Mode Memory Management,” in the Intel® 64 and IA-32Architectures Software Developer’s Manual, Volume 3A). When the D flag is set, the32-bit operand-size and address-size attributes are selected; when the flag is clear,the 16-bit size attributes are selected.
When the processor is executing in realaddress mode, virtual-8086 mode, or SMM, the default operand-size and addresssize attributes are always 16 bits.3-24 Vol. 1BASIC EXECUTION ENVIRONMENTThe operand-size attribute selects the size of operands. When the 16-bit operandsize attribute is in force, operands can generally be either 8 bits or 16 bits, and whenthe 32-bit operand-size attribute is in force, operands can generally be 8 bits or 32bits.The address-size attribute selects the sizes of addresses used to address memory:16 bits or 32 bits.
When the 16-bit address-size attribute is in force, segment offsetsand displacements are 16 bits. This restriction limits the size of a segment to 64KBytes. When the 32-bit address-size attribute is in force, segment offsets anddisplacements are 32 bits, allowing up to 4 GBytes to be addressed.The default operand-size attribute and/or address-size attribute can be overriddenfor a particular instruction by adding an operand-size and/or address-size prefix toan instruction. See Chapter 2, “Instruction Format,” in the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 3A.
The effect of this prefix appliesonly to the targeted instruction.Table 3-4 shows effective operand size and address size (when executing inprotected mode or compatibility mode) depending on the settings of the D flag andthe operand-size and address-size prefixes.Table 3-3. Effective Operand- and Address-Size AttributesD Flag in Code Segment Descriptor 00001111Operand-Size Prefix 66HNNYYNNYYAddress-Size Prefix 67HNYNYNYNYEffective Operand Size1616323232321616Effective Address Size1632163232163216NOTES:Y: Yes - this instruction prefix is present.N: No - this instruction prefix is not present.3.6.1Operand Size and Address Size in 64-Bit ModeIn 64-bit mode, the default address size is 64 bits and the default operand size is 32bits.
Defaults can be overridden using prefixes. Address-size and operand-sizeprefixes allow mixing of 32/64-bit data and 32/64-bit addresses on an instructionby-instruction basis. Table 3-4 shows valid combinations of the 66H instruction prefixand the REX.W prefix that may be used to specify operand-size overrides in 64-bitmode. Note that 16-bit addresses are not supported in 64-bit mode.REX prefixes consist of 4-bit fields that form 16 different values. The W-bit field in theREX prefixes is referred to as REX.W.
If the REX.W field is properly set, the prefixspecifies an operand size override to 64 bits. Note that software can still use theoperand-size 66H prefix to toggle to a 16-bit operand size. However, setting REX.Wtakes precedence over the operand-size prefix (66H) when both are used.Vol. 1 3-25BASIC EXECUTION ENVIRONMENTIn the case of SSE/SSE2/SSE3/SSSE3 SIMD instructions: the 66H, F2H, and F3Hprefixes are mandatory for opcode extensions.
In such a case, there is no interactionbetween a valid REX.W prefix and a 66H opcode extension prefix.See Chapter 2, “Instruction Format,” in the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 3A.Table 3-4. Effective Operand- and Address-Size Attributes in 64-Bit ModeL Flag in Code SegmentDescriptor11111111REX.W Prefix00001111Operand-Size Prefix 66HNNYYNNYYAddress-Size Prefix 67HNYNYNYNYEffective Operand Size3232161664646464Effective Address Size6432643264326432NOTES:Y: Yes - this instruction prefix is present.N: No - this instruction prefix is not present.3.7OPERAND ADDRESSINGIA-32 machine-instructions act on zero or more operands.
Some operands are specified explicitly and others are implicit. The data for a source operand can be locatedin:••••the instruction itself (an immediate operand)a registera memory locationan I/O portWhen an instruction returns data to a destination operand, it can be returned to:•••a registera memory locationan I/O port3.7.1Immediate OperandsSome instructions use data encoded in the instruction itself as a source operand.These operands are called immediate operands (or simply immediates).
For3-26 Vol. 1BASIC EXECUTION ENVIRONMENTexample, the following ADD instruction adds an immediate value of 14 to thecontents of the EAX register:ADD EAX, 14All arithmetic instructions (except the DIV and IDIV instructions) allow the sourceoperand to be an immediate value. The maximum value allowed for an immediateoperand varies among instructions, but can never be greater than the maximumvalue of an unsigned doubleword integer (232).3.7.2Register OperandsSource and destination operands can be any of the following registers, depending onthe instruction being executed:••••••32-bit general-purpose registers (EAX, EBX, ECX, EDX, ESI, EDI, ESP, or EBP)•••MMX registers (MM0 through MM7)••debug registers (DR0, DR1, DR2, DR3, DR6, and DR7)16-bit general-purpose registers (AX, BX, CX, DX, SI, DI, SP, or BP)8-bit general-purpose registers (AH, BH, CH, DH, AL, BL, CL, or DL)segment registers (CS, DS, SS, ES, FS, and GS)EFLAGS registerx87 FPU registers (ST0 through ST7, status word, control word, tag word, dataoperand pointer, and instruction pointer)XMM registers (XMM0 through XMM7) and the MXCSR registercontrol registers (CR0, CR2, CR3, and CR4) and system table pointer registers(GDTR, LDTR, IDTR, and task register)MSR registersSome instructions (such as the DIV and MUL instructions) use quadword operandscontained in a pair of 32-bit registers.
Register pairs are represented with a colonseparating them. For example, in the register pair EDX:EAX, EDX contains the highorder bits and EAX contains the low order bits of a quadword operand.Several instructions (such as the PUSHFD and POPFD instructions) are provided toload and store the contents of the EFLAGS register or to set or clear individual flagsin this register. Other instructions (such as the Jcc instructions) use the state of thestatus flags in the EFLAGS register as condition codes for branching or other decisionmaking operations.The processor contains a selection of system registers that are used to controlmemory management, interrupt and exception handling, task management,processor management, and debugging activities.
Some of these system registersare accessible by an application program, the operating system, or the executivethrough a set of system instructions. When accessing a system register with asystem instruction, the register is generally an implied operand of the instruction.Vol. 1 3-27BASIC EXECUTION ENVIRONMENT3.7.2.1Register Operands in 64-Bit ModeRegister operands in 64-bit mode can be any of the following:•64-bit general-purpose registers (RAX, RBX, RCX, RDX, RSI, RDI, RSP, RBP, orR8-R15)•32-bit general-purpose registers (EAX, EBX, ECX, EDX, ESI, EDI, ESP, EBP, orR8D-R15D)••16-bit general-purpose registers (AX, BX, CX, DX, SI, DI, SP, BP, or R8W-R15W)•••Segment registers (CS, DS, SS, ES, FS, and GS)•••MMX registers (MM0 through MM7)•••Debug registers (DR0, DR1, DR2, DR3, DR6, and DR7)8-bit general-purpose registers: AL, BL, CL, DL, SIL, DIL, SPL, BPL, and R8LR15L are available using REX prefixes; AL, BL, CL, DL, AH, BH, CH, DH areavailable without using REX prefixes.RFLAGS registerx87 FPU registers (ST0 through ST7, status word, control word, tag word, dataoperand pointer, and instruction pointer)XMM registers (XMM0 through XMM15) and the MXCSR registerControl registers (CR0, CR2, CR3, CR4, and CR8) and system table pointerregisters (GDTR, LDTR, IDTR, and task register)MSR registersRDX:RAX register pair representing a 128-bit operand3.7.3Memory OperandsSource and destination operands in memory are referenced by means of a segmentselector and an offset (see Figure 3-9).
Segment selectors specify the segmentcontaining the operand. Offsets specify the linear or effective address of the operand.Offsets can be 32 bits (represented by the notation m16:32) or 16 bits (representedby the notation m16:16).15SegmentSelector0310Offset (or Linear Address)Figure 3-9. Memory Operand Address3.7.3.1Memory Operands in 64-Bit ModeIn 64-bit mode, a memory operand can be referenced by a segment selector and anoffset. The offset can be 16 bits, 32 bits or 64 bits (see Figure 3-10).3-28 Vol. 1BASIC EXECUTION ENVIRONMENT15SegmentSelector0630Offset (or Linear Address)Figure 3-10. Memory Operand Address in 64-Bit Mode3.7.4Specifying a Segment SelectorThe segment selector can be specified either implicitly or explicitly.
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