Volume 1 Basic Architecture (794100), страница 22
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Whenusing a segmented memory model, some instructions assume that pointers in certainregisters are relative to specific segments. For instance, some instructions assumethat a pointer in the EBX register points to a memory location in the DS segment.3-14 Vol.
1BASIC EXECUTION ENVIRONMENT31General-Purpose Registers0EAXEBXECXEDXESIEDIEBPESPSegment Registers015CSDSSSESFSGSProgram Status and Control Register031EFLAGS31Instruction Pointer0EIPFigure 3-4. General System and Application Programming RegistersThe special uses of general-purpose registers by instructions are described inChapter 5, “Instruction Set Summary,” in this volume. See also: Chapter 3 andChapter 4 of Intel® 64 and IA-32 Architectures Software Developer’s Manual,Volumes 2A & 2B. The following is a summary of special uses:•••••EAX — Accumulator for operands and results dataEBX — Pointer to data in the DS segmentECX — Counter for string and loop operationsEDX — I/O pointerESI — Pointer to data in the segment pointed to by the DS register; sourcepointer for string operations•EDI — Pointer to data (or destination) in the segment pointed to by the ESregister; destination pointer for string operations•ESP — Stack pointer (in the SS segment)Vol.
1 3-15BASIC EXECUTION ENVIRONMENT•EBP — Pointer to data on the stack (in the SS segment)As shown in Figure 3-5, the lower 16 bits of the general-purpose registers mapdirectly to the register set found in the 8086 and Intel 286 processors and can bereferenced with the names AX, BX, CX, DX, BP, SI, DI, and SP.
Each of the lower twobytes of the EAX, EBX, ECX, and EDX registers can be referenced by the names AH,BH, CH, and DH (high bytes) and AL, BL, CL, and DL (low bytes).31General-Purpose Registers8 716 150 16-bit 32-bitAHALAXEAXBHBLBXEBXCHCLCXECXDLDXEDXDHBPEBPSIESIDIEDIESPSPFigure 3-5. Alternate General-Purpose Register Names3.4.1.1General-Purpose Registers in 64-Bit ModeIn 64-bit mode, there are 16 general purpose registers and the default operand sizeis 32 bits. However, general-purpose registers are able to work with either 32-bit or64-bit operands. If a 32-bit operand size is specified: EAX, EBX, ECX, EDX, EDI, ESI,EBP, ESP, R8D - R15D are available.
If a 64-bit operand size is specified: RAX, RBX,RCX, RDX, RDI, RSI, RBP, RSP, R8-R15 are available. R8D-R15D/R8-R15 representeight new general-purpose registers. All of these registers can be accessed at thebyte, word, dword, and qword level. REX prefixes are used to generate 64-bitoperand sizes or to reference registers R8-R15.Registers only available in 64-bit mode (R8-R15 and XMM8-XMM15) are preservedacross transitions from 64-bit mode into compatibility mode then back into 64-bitmode. However, values of R8-R15 and XMM8-XMM15 are undefined after transitionsfrom 64-bit mode through compatibility mode to legacy or real mode and then backthrough compatibility mode to 64-bit mode.3-16 Vol.
1BASIC EXECUTION ENVIRONMENTTable 3-2. Addressable General Purpose RegistersRegister TypeWithout REXWith REXByte RegistersAL, BL, CL, DL, AH, BH, CH,DHAL, BL, CL, DL, DIL, SIL, BPL, SPL,R8L - R15LWord RegistersAX, BX, CX, DX, DI, SI, BP, SPAX, BX, CX, DX, DI, SI, BP, SP, R8W R15WDoubleword RegistersEAX, EBX, ECX, EDX, EDI, ESI, EAX, EBX, ECX, EDX, EDI, ESI, EBP,EBP, ESPESP, R8D - R15DQuadword RegistersN.A.RAX, RBX, RCX, RDX, RDI, RSI,RBP, RSP, R8 - R15In 64-bit mode, there are limitations on accessing byte registers. An instructioncannot reference legacy high-bytes (for example: AH, BH, CH, DH) and one of thenew byte registers at the same time (for example: the low byte of the RAX register).However, instructions may reference legacy low-bytes (for example: AL, BL, CL orDL) and new byte registers at the same time (for example: the low byte of the R8register, or RBP). The architecture enforces this limitation by changing high-bytereferences (AH, BH, CH, DH) to low byte references (BPL, SPL, DIL, SIL: the low 8bits for RBP, RSP, RDI and RSI) for instructions using a REX prefix.When in 64-bit mode, operand size determines the number of valid bits in the destination general-purpose register:•64-bit operands generate a 64-bit result in the destination general-purposeregister.•32-bit operands generate a 32-bit result, zero-extended to a 64-bit result in thedestination general-purpose register.•8-bit and 16-bit operands generate an 8-bit or 16-bit result.
The upper 56 bits or48 bits (respectively) of the destination general-purpose register are not bemodified by the operation. If the result of an 8-bit or 16-bit operation is intendedfor 64-bit address calculation, explicitly sign-extend the register to the full64-bits.Because the upper 32 bits of 64-bit general-purpose registers are undefined in 32-bitmodes, the upper 32 bits of any general-purpose register are not preserved whenswitching from 64-bit mode to a 32-bit mode (to protected mode or compatibilitymode). Software must not depend on these bits to maintain a value after a 64-bit to32-bit mode switch.3.4.2Segment RegistersThe segment registers (CS, DS, SS, ES, FS, and GS) hold 16-bit segment selectors.A segment selector is a special pointer that identifies a segment in memory.
Toaccess a particular segment in memory, the segment selector for that segment mustbe present in the appropriate segment register.Vol. 1 3-17BASIC EXECUTION ENVIRONMENTWhen writing application code, programmers generally create segment selectorswith assembler directives and symbols.
The assembler and other tools then createthe actual segment selector values associated with these directives and symbols. Ifwriting system code, programmers may need to create segment selectors directly.See Chapter 3, “Protected-Mode Memory Management,” in the Intel® 64 and IA-32Architectures Software Developer’s Manual, Volume 3A.How segment registers are used depends on the type of memory management modelthat the operating system or executive is using.
When using the flat (unsegmented)memory model, segment registers are loaded with segment selectors that point tooverlapping segments, each of which begins at address 0 of the linear address space(see Figure 3-6). These overlapping segments then comprise the linear addressspace for the program. Typically, two overlapping segments are defined: one for codeand another for data and stacks. The CS segment register points to the codesegment and all the other segment registers point to the data and stack segment.When using the segmented memory model, each segment register is ordinarilyloaded with a different segment selector so that each segment register points to adifferent segment within the linear address space (see Figure 3-7). At any time, aprogram can thus access up to six segments in the linear address space.
To access asegment not pointed to by one of the segment registers, a program must first loadthe segment selector for the segment to be accessed into a segment register.Linear AddressSpace for ProgramSegment RegistersCSDSSSESFSGSThe segment selector ineach segment registerpoints to an overlappingsegment in the linearaddress space.OverlappingSegmentsof up to4 GBytesBeginning atAddress 0Figure 3-6. Use of Segment Registers for Flat Memory Model3-18 Vol.
1BASIC EXECUTION ENVIRONMENTCodeSegmentSegment RegistersCSDSSSESFSGSDataSegmentStackSegmentAll segmentsare mappedto the samelinear-addressspaceDataSegmentDataSegmentDataSegmentFigure 3-7. Use of Segment Registers in Segmented Memory ModelEach of the segment registers is associated with one of three types of storage: code,data, or stack. For example, the CS register contains the segment selector for thecode segment, where the instructions being executed are stored.
The processorfetches instructions from the code segment, using a logical address that consists ofthe segment selector in the CS register and the contents of the EIP register. The EIPregister contains the offset within the code segment of the next instruction to beexecuted. The CS register cannot be loaded explicitly by an application program.Instead, it is loaded implicitly by instructions or internal processor operations thatchange program control (such as, procedure calls, interrupt handling, or taskswitching).The DS, ES, FS, and GS registers point to four data segments. The availability offour data segments permits efficient and secure access to different types of datastructures. For example, four separate data segments might be created: one for thedata structures of the current module, another for the data exported from a higherlevel module, a third for a dynamically created data structure, and a fourth for datashared with another program. To access additional data segments, the applicationprogram must load segment selectors for these segments into the DS, ES, FS, andGS registers, as needed.The SS register contains the segment selector for the stack segment, where theprocedure stack is stored for the program, task, or handler currently being executed.All stack operations use the SS register to find the stack segment.
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