Volume 1 Basic Architecture (794100), страница 19
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The operating mode determineswhich instructions and architectural features are accessible:•Protected mode — This mode is the native state of the processor. Among thecapabilities of protected mode is the ability to directly execute “real-addressmode” 8086 software in a protected, multi-tasking environment.
This feature iscalled virtual-8086 mode, although it is not actually a processor mode. Virtual8086 mode is actually a protected mode attribute that can be enabled for anytask.•Real-address mode — This mode implements the programming environment ofthe Intel 8086 processor with extensions (such as the ability to switch toprotected or system management mode).
The processor is placed in real-addressmode following power-up or a reset.•System management mode (SMM) — This mode provides an operatingsystem or executive with a transparent mechanism for implementing platformspecific functions such as power management and system security. Theprocessor enters SMM when the external SMM interrupt pin (SMI#) is activatedor an SMI is received from the advanced programmable interrupt controller(APIC).In SMM, the processor switches to a separate address space while saving thebasic context of the currently running program or task. SMM-specific code maythen be executed transparently. Upon returning from SMM, the processor isplaced back into its state prior to the system management interrupt.
SMM wasintroduced with the Intel386™ SL and Intel486™ SL processors and became astandard IA-32 feature with the Pentium processor family.Vol. 1 3-1BASIC EXECUTION ENVIRONMENT3.1.1Intel® 64 ArchitectureIntel 64 architecture adds IA-32e mode. IA-32e mode has two sub-modes. Theseare:•Compatibility mode (sub-mode of IA-32e mode) — Compatibility modepermits most legacy 16-bit and 32-bit applications to run without re-compilationunder a 64-bit operating system. For brevity, the compatibility sub-mode isreferred to as compatibility mode in IA-32 architecture. The executionenvironment of compatibility mode is the same as described in Section 3.2.Compatibility mode also supports all of the privilege levels that are supported in64-bit and protected modes. Legacy applications that run in Virtual 8086 mode oruse hardware task management will not work in this mode.Compatibility mode is enabled by the operating system (OS) on a code segmentbasis.
This means that a single 64-bit OS can support 64-bit applications runningin 64-bit mode and support legacy 32-bit applications (not recompiled for64-bits) running in compatibility mode.Compatibility mode is similar to 32-bit protected mode. Applications access onlythe first 4 GByte of linear-address space. Compatibility mode uses 16-bit and 32bit address and operand sizes.
Like protected mode, this mode allows applications to access physical memory greater than 4 GByte using PAE (PhysicalAddress Extensions).•64-bit mode (sub-mode of IA-32e mode) — This mode enables a 64-bitoperating system to run applications written to access 64-bit linear addressspace. For brevity, the 64-bit sub-mode is referred to as 64-bit mode in IA-32architecture.64-bit mode extends the number of general purpose registers and SIMDextension registers from 8 to 16. General purpose registers are widened to 64bits.
The mode also introduces a new opcode prefix (REX) to access the registerextensions. See Section 3.2.1 for a detailed description.64-bit mode is enabled by the operating system on a code-segment basis. Itsdefault address size is 64 bits and its default operand size is 32 bits. The defaultoperand size can be overridden on an instruction-by-instruction basis using a REXopcode prefix in conjunction with an operand size override prefix.REX prefixes allow a 64-bit operand to be specified when operating in 64-bitmode.
By using this mechanism, many existing instructions have been promotedto allow the use of 64-bit registers and 64-bit addresses.3.2OVERVIEW OF THE BASIC EXECUTIONENVIRONMENTAny program or task running on an IA-32 processor is given a set of resources forexecuting instructions and for storing code, data, and state information. These3-2 Vol. 1BASIC EXECUTION ENVIRONMENTresources (described briefly in the following paragraphs and shown in Figure 3-1)make up the basic execution environment for an IA-32 processor.An Intel 64 processor supports the basic execution environment of an IA-32processor, and a similar environment under IA-32e mode that can execute 64-bitprograms (64-bit sub-mode) and 32-bit programs (compatibility sub-mode).The basic execution environment is used jointly by the application programs and theoperating system or executive running on the processor.•Address space — Any task or program running on an IA-32 processor canaddress a linear address space of up to 4 GBytes (232 bytes) and a physicaladdress space of up to 64 GBytes (236 bytes).
See Section 3.3.6, “ExtendedPhysical Addressing in Protected Mode,” for more information about addressingan address space greater than 4 GBytes.•Basic program execution registers — The eight general-purpose registers,the six segment registers, the EFLAGS register, and the EIP (instruction pointer)register comprise a basic execution environment in which to execute a set ofgeneral-purpose instructions.
These instructions perform basic integer arithmeticon byte, word, and doubleword integers, handle program flow control, operate onbit and byte strings, and address memory. See Section 3.4, “Basic ProgramExecution Registers,” for more information about these registers.•x87 FPU registers — The eight x87 FPU data registers, the x87 FPU controlregister, the status register, the x87 FPU instruction pointer register, the x87 FPUoperand (data) pointer register, the x87 FPU tag register, and the x87 FPU opcoderegister provide an execution environment for operating on single-precision,double-precision, and double extended-precision floating-point values, wordintegers, doubleword integers, quadword integers, and binary coded decimal(BCD) values.
See Section 8.1, “x87 FPU Execution Environment,” for moreinformation about these registers.•MMX registers — The eight MMX registers support execution of singleinstruction, multiple-data (SIMD) operations on 64-bit packed byte, word, anddoubleword integers. See Section 9.2, “The MMX Technology ProgrammingEnvironment,” for more information about these registers.•XMM registers — The eight XMM data registers and the MXCSR register supportexecution of SIMD operations on 128-bit packed single-precision and doubleprecision floating-point values and on 128-bit packed byte, word, doubleword,and quadword integers. See Section 10.2, “SSE Programming Environment,” formore information about these registers.Vol.
1 3-3BASIC EXECUTION ENVIRONMENTBasic Program Execution RegistersAddress Space*232 -1Eight 32-bitRegistersGeneral-Purpose RegistersSix 16-bitRegistersSegment Registers32-bitsEFLAGS Register32-bitsEIP (Instruction Pointer Register)FPU RegistersFloating-PointData RegistersEight 80-bitRegisters016 bitsControl Register16 bitsStatus Register16 bitsTag Register*The address space can beflat or segmented. Usingthe physical addressextension mechanism, aphysical address space of236 - 1 can be addressed.Opcode Register (11-bits)48 bitsFPU Instruction Pointer Register48 bitsFPU Data (Operand) Pointer RegisterMMX RegistersEight 64-bitRegistersMMX RegistersXMM RegistersEight 128-bitRegistersXMM Registers32-bitsMXCSR RegisterFigure 3-1.
IA-32 Basic Execution Environment for Non-64-bit Modes3-4 Vol. 1BASIC EXECUTION ENVIRONMENT•Stack — To support procedure or subroutine calls and the passing of parametersbetween procedures or subroutines, a stack and stack management resourcesare included in the execution environment.
The stack (not shown in Figure 3-1) islocated in memory. See Section 6.2, “Stacks,” for more information about stackstructure.In addition to the resources provided in the basic execution environment, the IA-32architecture provides the following resources as part of its system-level architecture.They provide extensive support for operating-system and system-development software. Except for the I/O ports, the system resources are described in detail in theIntel® 64 and IA-32 Architectures Software Developer’s Manual, Volumes 3A & 3B.•I/O ports — The IA-32 architecture supports a transfers of data to and frominput/output (I/O) ports. See Chapter 13, “Input/Output,” in this volume.•Control registers — The five control registers (CR0 through CR4) determine theoperating mode of the processor and the characteristics of the currentlyexecuting task.
See Chapter 2, “System Architecture Overview,” in the Intel® 64and IA-32 Architectures Software Developer’s Manual, Volume 3A.•Memory management registers — The GDTR, IDTR, task register, and LDTRspecify the locations of data structures used in protected mode memorymanagement. See Chapter 2, “System Architecture Overview,” in the Intel® 64and IA-32 Architectures Software Developer’s Manual, Volume 3A.•Debug registers — The debug registers (DR0 through DR7) control and allowmonitoring of the processor’s debugging operations.
See Chapter 18, “Debuggingand Performance Monitoring,” in the Intel® 64 and IA-32 Architectures SoftwareDeveloper’s Manual, Volume 3B.•Memory type range registers (MTRRs) — The MTRRs are used to assignmemory types to regions of memory. See the sections on MTRRs in the Intel® 64and IA-32 Architectures Software Developer’s Manual, Volume 3B.•Machine specific registers (MSRs) — The processor provides a variety ofmachine specific registers that are used to control and report on processorperformance. Virtually all MSRs handle system related functions and are notaccessible to an application program.
One exception to this rule is the timestamp counter. The MSRs are described in Appendix B, “Model-Specific Registers(MSRs),” of the Intel® 64 and IA-32 Architectures Software Developer’s Manual,Volume 3B.•Machine check registers — The machine check registers consist of a set ofcontrol, status, and error-reporting MSRs that are used to detect and report onhardware (machine) errors. See Chapter 14, “Machine-Check Architecture,” ofthe Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 3A.•Performance monitoring counters — The performance monitoring countersallow processor performance events to be monitored.
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