Volume 1 Basic Architecture (794100), страница 15
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The Dual-Core Intel Xeon processor includes dualcore technology. The Intel Xeon processor 70xx series includes Intel VirtualizationTechnology.The Intel Xeon processor 5100 series introduces power-efficient, high performanceIntel Core microarchitecture. This processor is based on Intel 64 architecture; itincludes Intel Virtualization Technology and dual-core technology. The Intel Xeonprocessor 3000 series are also based on Intel Core microarchitecture. The Intel Xeonprocessor 5300 series introduces four processor cores in a physical package, they arealso based on Intel Core microarchitecture.2-4 Vol.
1INTEL® 64 AND IA-32 ARCHITECTURES2.1.9The Intel® Pentium® M Processor (2003-Current)The Intel Pentium M processor family is a high performance, low power mobileprocessor family with microarchitectural enhancements over previous generations ofIA-32 Intel mobile processors. This family is designed for extending battery life andseamless integration with platform innovations that enable new usage models (suchas extended mobility, ultra thin form-factors, and integrated wireless networking).Its enhanced microarchitecture includes:••Support for Intel Architecture with Dynamic Execution••On-die, primary 32-KByte instruction cache and 32-KByte write-back data cache••Advanced Branch Prediction and Data Prefetch Logic••A 400 or 533 MHz, Source-Synchronous Processor System BusA high performance, low-power core manufactured using Intel’s advancedprocess technology with copper interconnectOn-die, second-level cache (up to 2 MByte) with Advanced Transfer Cache ArchitectureSupport for MMX technology, Streaming SIMD instructions, and the SSE2instruction setAdvanced power management using Enhanced Intel SpeedStep® technology2.1.10The Intel® Pentium® Processor Extreme Edition (2005-2007)The Intel Pentium processor Extreme Edition introduced dual-core technology.
Thistechnology provides advanced hardware multi-threading support. The processor isbased on Intel NetBurst microarchitecture and supports SSE, SSE2, SSE3, HyperThreading Technology, and Intel 64 architecture.See also:••••••Section 2.2.2, “Intel NetBurst® Microarchitecture”Section 2.2.3, “Intel® Core™ Microarchitecture”Section 2.2.4, “SIMD Instructions”Section 2.2.5, “Hyper-Threading Technology”Section 2.2.6, “Multi-Core Technology”Section 2.2.7, “Intel® 64 Architecture”2.1.11The Intel® Core™ Duo and Intel® Core™ Solo Processors(2006-Current)The Intel Core Duo processor offers power-efficient, dual-core performance with alow-power design that extends battery life.
This family and the single-core Intel CoreVol. 1 2-5INTEL® 64 AND IA-32 ARCHITECTURESSolo processor offer microarchitectural enhancements over Pentium M processorfamily.Its enhanced microarchitecture includes:•Intel® Smart Cache which allows for efficient data sharing between twoprocessor cores••Improved decoding and SIMD execution•Intel® Advanced Thermal Manager which features digital thermal sensorinterfaces•Support for power-optimized 667 MHz busIntel® Dynamic Power Coordination and Enhanced Intel® Deeper Sleep to reducepower consumptionThe dual-core Intel Xeon processor LV is based on the same microarchitecture asIntel Core Duo processor, and supports IA-32 architecture.2.1.12The Intel® Xeon® Processor 5100 Series and Intel® Core™2Processor Family (2006-Current)The Intel Xeon processor 3000, 5100, and 5300 series, Intel Core 2 Extreme, IntelCore 2 Quad processors, and Intel Core 2 Duo processor family support Intel 64architecture; and they are based on the high-performance, power-efficient Intel®Core microarchitecture.
The Intel Core microarchitecture includes the following innovative features:•Intel® Wide Dynamic Execution to increase performance and executionthroughput••Intel® Intelligent Power Capability to reduce power consumption•Intel® Smart Memory Access to increase data bandwidth and hide latency ofmemory accesses•Intel® Advanced Digital Media Boost which improves application performanceusing multiple generations of Streaming SIMD extensionsIntel® Advanced Smart Cache which allows for efficient data sharing betweentwo processor coresThe Intel Xeon processor 5300 series, Intel Core 2 Extreme Quad-core processor, andIntel Core 2 Quad processors support Intel quad-core technology.2.2MORE ON SPECIFIC ADVANCESThe following sections provide more information on major innovations.2-6 Vol.
1INTEL® 64 AND IA-32 ARCHITECTURES2.2.1P6 Family MicroarchitectureThe Pentium Pro processor introduced a new microarchitecture commonly referred toas P6 processor microarchitecture. The P6 processor microarchitecture was laterenhanced with an on-die, Level 2 cache, called Advanced Transfer Cache.The microarchitecture is a three-way superscalar, pipelined architecture. Three-waysuperscalar means that by using parallel processing techniques, the processor is ableon average to decode, dispatch, and complete execution of (retire) three instructionsper clock cycle.
To handle this level of instruction throughput, the P6 processor familyuses a decoupled, 12-stage superpipeline that supports out-of-order instructionexecution.Figure 2-1 shows a conceptual view of the P6 processor microarchitecture pipelinewith the Advanced Transfer Cache enhancement.Vol. 1 2-7INTEL® 64 AND IA-32 ARCHITECTURESSystem BusFrequently usedBus Unit2nd Level CacheOn-die, 8-wayLess frequently used1st Level Cache4-way, low latencyFront EndFetch/DecodeExecutionInstructionCacheMicrocodeROMExecutionOut-of-OrderCoreRetirementBranch History UpdateBTSs/Branch PredictionOM16520Figure 2-1. The P6 Processor Microarchitecture with Advanced Transfer CacheEnhancementTo ensure a steady supply of instructions and data for the instruction execution pipeline, the P6 processor microarchitecture incorporates two cache levels.
The Level 1cache provides an 8-KByte instruction cache and an 8-KByte data cache, both closelycoupled to the pipeline. The Level 2 cache provides 256-KByte, 512-KByte, or1-MByte static RAM that is coupled to the core processor through a full clock-speed64-bit cache bus.The centerpiece of the P6 processor microarchitecture is an out-of-order executionmechanism called dynamic execution. Dynamic execution incorporates three dataprocessing concepts:•Deep branch prediction allows the processor to decode instructions beyondbranches to keep the instruction pipeline full. The P6 processor familyimplements highly optimized branch prediction algorithms to predict the directionof the instruction.•Dynamic data flow analysis requires real-time analysis of the flow of datathrough the processor to determine dependencies and to detect opportunities forout-of-order instruction execution. The out-of-order execution core can monitormany instructions and execute these instructions in the order that best optimizes2-8 Vol.
1INTEL® 64 AND IA-32 ARCHITECTURESthe use of the processor’s multiple execution units, while maintaining the dataintegrity.•Speculative execution refers to the processor’s ability to execute instructionsthat lie beyond a conditional branch that has not yet been resolved, andultimately to commit the results in the order of the original instruction stream.
Tomake speculative execution possible, the P6 processor microarchitecturedecouples the dispatch and execution of instructions from the commitment ofresults. The processor’s out-of-order execution core uses data-flow analysis toexecute all available instructions in the instruction pool and store the results intemporary registers.
The retirement unit then linearly searches the instructionpool for completed instructions that no longer have data dependencies with otherinstructions or unresolved branch predictions. When completed instructions arefound, the retirement unit commits the results of these instructions to memoryand/or the IA-32 registers (the processor’s eight general-purpose registers andeight x87 FPU data registers) in the order they were originally issued and retiresthe instructions from the instruction pool.2.2.2Intel NetBurst® MicroarchitectureThe Intel NetBurst microarchitecture provides:•The Rapid Execution Engine— Arithmetic Logic Units (ALUs) run at twice the processor frequency— Basic integer operations can dispatch in 1/2 processor clock tick•Hyper-Pipelined Technology— Deep pipeline to enable industry-leading clock rates for desktop PCs andservers— Frequency headroom and scalability to continue leadership into the future•Advanced Dynamic Execution— Deep, out-of-order, speculative execution engine••Up to 126 instructions in flightUp to 48 loads and 24 stores in pipeline1— Enhanced branch prediction capability••••Reduces the misprediction penalty associated with deeper pipelinesAdvanced branch prediction algorithm4K-entry branch target arrayNew cache subsystem1.
Intel 64 and IA-32 processors based on the Intel NetBurst microarchitecture at 90 nm processcan handle more than 24 stores in flight.Vol. 1 2-9INTEL® 64 AND IA-32 ARCHITECTURES— First level caches••Advanced Execution Trace Cache stores decoded instructionsExecution Trace Cache removes decoder latency from main executionloops•Execution Trace Cache integrates path of program execution flow into asingle line•Low latency data cache— Second level cache•••Full-speed, unified 8-way Level 2 on-die Advance Transfer CacheBandwidth and performance increases with processor frequencyHigh-performance, quad-pumped bus interface to the Intel NetBurst microarchitecture system bus— Supports quad-pumped, scalable bus clock to achieve up to 4X effectivespeed— Capable of delivering up to 8.5 GBytes of bandwidth per second••Superscalar issue to enable parallelism•64-byte cache line size (transfers data up to two lines per sector)Expanded hardware registers with renaming to avoid register name spacelimitationsFigure 2-2 is an overview of the Intel NetBurst microarchitecture.
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