Volume 1 Basic Architecture (794100), страница 12
Текст из файла (страница 12)
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . E-9CMPPS.NEQ, CMPSS.NEQ, CMPPS.UNORD, CMPSS.UNORD, CMPPD.NEQ,CMPSD.NEQ, CMPPD.UNORD, CMPSD.UNORD . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . E-9CMPPS.LT, CMPSS.LT, CMPPS.LE, CMPSS.LE, CMPPD.LT, CMPSD.LT,CMPPD.LE, CMPSD.LE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . E-9CMPPS.NLT, CMPSS.NLT, CMPPS.NLE, CMPSS.NLE, CMPPD.NLT,CMPSD.NLT, CMPPD.NLE, CMPSD.NLE . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . E-10COMISS, COMISD. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . E-10UCOMISS, UCOMISD .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . E-10CVTPS2PI, CVTSS2SI, CVTTPS2PI, CVTTSS2SI, CVTPD2PI, CVTSD2SI,CVTTPD2PI, CVTTSD2SI, CVTPS2DQ, CVTTPS2DQ, CVTPD2DQ, CVTTPD2DQ . . . E-11MAXPS, MAXSS, MINPS, MINSS, MAXPD, MAXSD, MINPD, MINSD .
. . . . . . . . . . . . . . . E-11SQRTPS, SQRTSS, SQRTPD, SQRTSD. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . E-11CVTPS2PD, CVTSS2SD. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . E-12CVTPD2PS, CVTSD2SS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . E-12#I - Invalid Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . E-13#Z - Divide-by-Zero. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . E-16#D - Denormal Operand . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . E-17#O - Numeric Overflow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . E-18#U - Numeric Underflow . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . E-20#P - Inexact Result (Precision) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . E-21Vol. 1 xxiCONTENTSPAGExxii Vol. 1CHAPTER 1ABOUT THIS MANUALThe Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 1:Basic Architecture (order number 253665) is part of a set that describes the architecture and programming environment of Intel® 64 and IA-32 architecture processors.Other volumes in this set are:•The Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volumes2A & 2B: Instruction Set Reference (order numbers 253666 and 253667).•The Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volumes3A & 3B: System Programming Guide (order number 253668 and 253669).The Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 1,describes the basic architecture and programming environment of Intel 64 and IA-32processors.
The Intel® 64 and IA-32 Architectures Software Developer’s Manual,Volumes 2A & 2B, describe the instruction set of the processor and the opcode structure. These volumes apply to application programmers and to programmers whowrite operating systems or executives. The Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volumes 3A & 3B, describe the operating-system supportenvironment of Intel 64 and IA-32 processors.
These volumes target operatingsystem and BIOS designers. In addition, the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 3B, addresses the programming environment forclasses of software that host operating systems.1.1INTEL® 64 AND IA-32 PROCESSORS COVERED INTHIS MANUALThis manual set includes information pertaining primarily to the most recent Intel 64and IA-32 processors, which include:••••••••••Pentium® processorsP6 family processorsPentium® 4 processorsPentium® M processorsIntel® Xeon® processorsPentium® D processorsPentium® processor Extreme Editions64-bit Intel® Xeon® processorsIntel® CoreTM Duo processorIntel® CoreTM Solo processorVol. 1 1-1ABOUT THIS MANUAL•••••••••Dual-Core Intel® Xeon® processor LVIntel® CoreTM2 Duo processorIntel® CoreTM2 Quad processorIntel® Xeon® processor 3000 seriesIntel® Xeon® processor 5100 seriesIntel® Xeon® processor 5300 seriesIntel® CoreTM2 Extreme processorIntel® CoreTM2 Extreme Quad-core processorIntel® Xeon® processor 7100 seriesP6 family processors are IA-32 processors based on the P6 family microarchitecture.This includes the Pentium® Pro, Pentium® II, Pentium® III, and Pentium® III Xeon®processors.The Pentium® 4, Pentium® D, and Pentium® processor Extreme Editions are basedon the Intel NetBurst® microarchitecture.
Most early Intel® Xeon® processors arebased on the Intel NetBurst® microarchitecture.The Intel® CoreTM Duo, Intel® CoreTM Solo and dual-core Intel® Xeon® processor LVare based on an improved Pentium® M processor microarchitecture.The Intel® Xeon® processor 3000, 5100, and 5300 series, Intel® CoreTM2 Duo,Intel® CoreTM2 Quad, and Intel® CoreTM2 Extreme processors are based on Intel®CoreTM microarchitecture.P6 family, Pentium® M, Intel® CoreTM Solo, Intel® CoreTM Duo processors, dual-coreIntel® Xeon® processor LV, and early generations of Pentium 4 and Intel Xeonprocessors support IA-32 architecture.The Intel® Xeon® processor 3000, 5100, 5300 series, Intel® CoreTM2 Duo, Intel®CoreTM2 Extreme processors, Intel Core 2 Quad processors, newer generations ofPentium 4 and Intel Xeon processor family support Intel® 64 architecture.IA-32 architecture is the instruction set architecture and programming environmentfor Intel's 32-bit microprocessors.Intel® 64 architecture is the instruction set architecture and programming environment which is the superset of Intel’s 32-bit and 64-bit architectures.
It is compatiblewith the IA-32 architecture.1.2OVERVIEW OF VOLUME 1: BASIC ARCHITECTUREA description of this manual’s content follows:Chapter 1 — About This Manual. Gives an overview of all five volumes of theIntel® 64 and IA-32 Architectures Software Developer’s Manual.
It also describesthe notational conventions in these manuals and lists related Intel manuals anddocumentation of interest to programmers and hardware designers.1-2 Vol. 1ABOUT THIS MANUALChapter 2 — Intel® 64 and IA-32 Architectures. Introduces the Intel 64 andIA-32 architectures along with the families of Intel processors that are based onthese architectures. It also gives an overview of the common features found in theseprocessors and brief history of the Intel 64 and IA-32 architectures.Chapter 3 — Basic Execution Environment. Introduces the models of memoryorganization and describes the register set used by applications.Chapter 4 — Data Types. Describes the data types and addressing modes recognized by the processor; provides an overview of real numbers and floating-pointformats and of floating-point exceptions.Chapter 5 — Instruction Set Summary.
Lists all Intel 64 and IA-32 instructions,divided into technology groups.Chapter 6 — Procedure Calls, Interrupts, and Exceptions. Describes the procedure stack and mechanisms provided for making procedure calls and for servicinginterrupts and exceptions.Chapter 7 — Programming with General-Purpose Instructions. Describesbasic load and store, program control, arithmetic, and string instructions thatoperate on basic data types, general-purpose and segment registers; also describessystem instructions that are executed in protected mode.Chapter 8 — Programming with the x87 FPU.
Describes the x87 floating-pointunit (FPU), including floating-point registers and data types; gives an overview of thefloating-point instruction set and describes the processor's floating-point exceptionconditions.Chapter 9 — Programming with Intel® MMX™ Technology. Describes IntelMMX technology, including MMX registers and data types; also provides an overviewof the MMX instruction set.Chapter 10 — Programming with Streaming SIMD Extensions (SSE).Describes SSE extensions, including XMM registers, the MXCSR register, and packedsingle-precision floating-point data types; provides an overview of the SSE instruction set and gives guidelines for writing code that accesses the SSE extensions.Chapter 11 — Programming with Streaming SIMD Extensions 2 (SSE2).Describes SSE2 extensions, including XMM registers and packed double-precisionfloating-point data types; provides an overview of the SSE2 instruction set and givesguidelines for writing code that accesses SSE2 extensions.
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