Volume 1 Basic Architecture (794100), страница 13

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This chapter alsodescribes SIMD floating-point exceptions that can be generated with SSE and SSE2instructions. It also provides general guidelines for incorporating support for SSE andSSE2 extensions into operating system and applications code.Chapter 12 — Programming with SSE3 and Supplemental SSE3. DescribesSSE3 extensions; provides an overview of the SSE3 instruction set, SupplementalSSE3 and guidelines for writing code that accesses these extensions.Chapter 13 — Input/Output.

Describes the processor’s I/O mechanism, includingI/O port addressing, I/O instructions, and I/O protection mechanisms.Vol. 1 1-3ABOUT THIS MANUALChapter 14 — Processor Identification and Feature Determination. Describeshow to determine the CPU type and features available in the processor.Appendix A — EFLAGS Cross-Reference.

Summarizes how the IA-32 instructionsaffect the flags in the EFLAGS register.Appendix B — EFLAGS Condition Codes. Summarizes how conditional jump,move, and ‘byte set on condition code’ instructions use condition code flags (OF, CF,ZF, SF, and PF) in the EFLAGS register.Appendix C — Floating-Point Exceptions Summary. Summarizes exceptionsraised by the x87 FPU floating-point and SSE/SSE2/SSE3 floating-point instructions.Appendix D — Guidelines for Writing x87 FPU Exception Handlers.

Describeshow to design and write MS-DOS* compatible exception handling facilities for FPUexceptions (includes software and hardware requirements and assembly-languagecode examples). This appendix also describes general techniques for writing robustFPU exception handlers.Appendix E — Guidelines for Writing SIMD Floating-Point ExceptionHandlers. Gives guidelines for writing exception handlers for exceptions generatedby SSE/SSE2/SSE3 floating-point instructions.1.3NOTATIONAL CONVENTIONSThis manual uses specific notation for data-structure formats, for symbolic representation of instructions, and for hexadecimal and binary numbers. This notation isdescribed below.1.3.1Bit and Byte OrderIn illustrations of data structures in memory, smaller addresses appear toward thebottom of the figure; addresses increase toward the top. Bit positions are numberedfrom right to left.

The numerical value of a set bit is equal to two raised to the powerof the bit position. Intel 64 and IA-32 processors are “little endian” machines; thismeans the bytes of a word are numbered starting from the least significant byte. SeeFigure 1-1.1-4 Vol. 1ABOUT THIS MANUALHighestAddressData Structure3224 23Byte 316 15Byte 28 7Byte 10Byte 0Bit offset2824201612840LowestAddressByte OffsetFigure 1-1.

Bit and Byte Order1.3.2Reserved Bits and Software CompatibilityIn many register and memory layout descriptions, certain bits are marked asreserved. When bits are marked as reserved, it is essential for compatibility withfuture processors that software treat these bits as having a future, though unknown,effect. The behavior of reserved bits should be regarded as not only undefined, butunpredictable.Software should follow these guidelines in dealing with reserved bits:•Do not depend on the states of any reserved bits when testing the values ofregisters that contain such bits.

Mask out the reserved bits before testing.•Do not depend on the states of any reserved bits when storing to memory or to aregister.••Do not depend on the ability to retain information written into any reserved bits.When loading a register, always load the reserved bits with the values indicatedin the documentation, if any, or reload them with values previously read from thesame register.NOTEAvoid any software dependence upon the state of reserved bits inIntel 64 and IA-32 registers. Depending upon the values of reservedregister bits will make software dependent upon the unspecifiedmanner in which the processor handles these bits. Programs thatdepend upon reserved values risk incompatibility with futureprocessors.Vol.

1 1-5ABOUT THIS MANUAL1.3.2.1Instruction OperandsWhen instructions are represented symbolically, a subset of the IA-32 assemblylanguage is used. In this subset, an instruction has the following format:label: mnemonic argument1, argument2, argument3where:••A label is an identifier which is followed by a colon.•The operands argument1, argument2, and argument3 are optional. Theremay be from zero to three operands, depending on the opcode. When present,they take the form of either literals or identifiers for data items. Operandidentifiers are either reserved names of registers or are assumed to be assignedto data items declared in another part of the program (which may not be shownin the example).A mnemonic is a reserved name for a class of instruction opcodes which havethe same function.When two operands are present in an arithmetic or logical instruction, the rightoperand is the source and the left operand is the destination.For example:LOADREG: MOV EAX, SUBTOTALIn this example, LOADREG is a label, MOV is the mnemonic identifier of an opcode,EAX is the destination operand, and SUBTOTAL is the source operand.

Someassembly languages put the source and destination in reverse order.1.3.3Hexadecimal and Binary NumbersBase 16 (hexadecimal) numbers are represented by a string of hexadecimal digitsfollowed by the character H (for example, 0F82EH). A hexadecimal digit is a character from the following set: 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, A, B, C, D, E, and F.Base 2 (binary) numbers are represented by a string of 1s and 0s, sometimesfollowed by the character B (for example, 1010B). The “B” designation is only used insituations where confusion as to the type of number might arise.1.3.4Segmented AddressingThe processor uses byte addressing.

This means memory is organized and accessedas a sequence of bytes. Whether one or more bytes are being accessed, a byteaddress is used to locate the byte or bytes memory. The range of memory that canbe addressed is called an address space.The processor also supports segmented addressing. This is a form of addressingwhere a program may have many independent address spaces, called segments.1-6 Vol. 1ABOUT THIS MANUALFor example, a program can keep its code (instructions) and stack in separatesegments.

Code addresses would always refer to the code space, and stackaddresses would always refer to the stack space. The following notation is used tospecify a byte address within a segment:Segment-register:Byte-addressFor example, the following segment address identifies the byte at address FF79H inthe segment pointed by the DS register:DS:FF79HThe following segment address identifies an instruction address in the code segment.The CS register points to the code segment and the EIP register contains the addressof the instruction.CS:EIP1.3.5A New Syntax for CPUID, CR, and MSR ValuesObtain feature flags, status, and system information by using the CPUID instruction,by checking control register bits, and by reading model-specific registers. We aremoving toward a new syntax to represent this information.

See Figure 1-2.Vol. 1 1-7ABOUT THIS MANUAL&38,',QSXWDQG2XWSXW&38,'+(&;66(>ELW@ ,QSXWYDOXHVIRU($;(&;UHJLVWHUV,IRQO\RQHYDOXH($;LVLPSOLHG2XWSXWUHJLVWHUDQGIHDWXUHIODJRUILHOGQDPHZLWKELWSRVLWLRQV9DOXHRUUDQJHRIRXWSXW&RQWURO5HJLVWHU9DOXHV&526);65>ELW@ ([DPSOH&5QDPH)HDWXUHIODJRUILHOGQDPHZLWKELWSRVLWLRQV9DOXHRUUDQJHRIRXWSXW0RGHO6SHFLILF5HJLVWHU9DOXHV,$B0,6&B(1$%/(6(1$%/()23&2'(>ELW@ ([DPSOH065QDPH)HDWXUHIODJRUILHOGQDPHZLWKELWSRVLWLRQV9DOXHRUUDQJHRIRXWSXW20Figure 1-2. Syntax for CPUID, CR, and MSR Data Presentation1.3.6ExceptionsAn exception is an event that typically occurs when an instruction causes an error.For example, an attempt to divide by zero generates an exception.

However, someexceptions, such as breakpoints, occur under other conditions. Some types of exceptions may provide error codes. An error code reports additional information about theerror. An example of the notation used to show an exception and error code is shownbelow:#PF(fault code)1-8 Vol. 1ABOUT THIS MANUALThis example refers to a page-fault exception under conditions where an error codenaming a type of fault is reported. Under some conditions, exceptions that produceerror codes may not be able to report an accurate code. In this case, the error codeis zero, as shown below for a general-protection exception:#GP(0)1.4RELATED LITERATURELiterature related to Intel 64 and IA-32 processors is listed on-line at:http://developer.intel.com/products/processor/manuals/index.htmSome of the documents listed at this web site can be viewed on-line; others can beordered.

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