Volume 1 Basic Architecture (794100), страница 21
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In 64-bitmode, there is architectural support for 64-bit linear address space. However,processors supporting Intel 64 architecture may implement less than 64-bits (seeSection 3.3.7.1). The linear address space is mapped into the processor physicaladdress space through the PAE paging mechanism.3.3.4Modes of Operation vs. Memory ModelWhen writing code for an IA-32 or Intel 64 processor, a programmer needs to knowthe operating mode the processor is going to be in when executing the code and thememory model being used.
The relationship between operating modes and memorymodels is as follows:•Protected mode — When in protected mode, the processor can use any of thememory models described in this section. (The real-addressing mode memorymodel is ordinarily used only when the processor is in the virtual-8086 mode.)The memory model used depends on the design of the operating system orexecutive.
When multitasking is implemented, individual tasks can use differentmemory models.3-10 Vol. 1BASIC EXECUTION ENVIRONMENT•Real-address mode — When in real-address mode, the processor only supportsthe real-address mode memory model.•System management mode — When in SMM, the processor switches to aseparate address space, called the system management RAM (SMRAM). Thememory model used to address bytes in this address space is similar to the realaddress mode model. See Chapter 24, “System Management,” in the Intel® 64and IA-32 Architectures Software Developer’s Manual, Volume 3B, for moreinformation on the memory model used in SMM.•Compatibility mode — Software that needs to run in compatibility mode shouldobserve the same memory model as those targeted to run in 32-bit protectedmode.
The effect of segmentation is the same as it is in 32-bit protected modesemantics.•64-bit mode — Segmentation is generally (but not completely) disabled,creating a flat 64-bit linear-address space. Specifically, the processor treats thesegment base of CS, DS, ES, and SS as zero in 64-bit mode (this makes a linearaddress equal an effective address). Segmented and real address modes are notavailable in 64-bit mode.3.3.532-Bit and 16-Bit Address and Operand SizesIA-32 processors in protected mode can be configured for 32-bit or 16-bit addressand operand sizes. With 32-bit address and operand sizes, the maximum linearaddress or segment offset is FFFFFFFFH (232-1); operand sizes are typically 8 bits or32 bits.
With 16-bit address and operand sizes, the maximum linear address orsegment offset is FFFFH (216-1); operand sizes are typically 8 bits or 16 bits.When using 32-bit addressing, a logical address (or far pointer) consists of a 16-bitsegment selector and a 32-bit offset; when using 16-bit addressing, an addressconsists of a 16-bit segment selector and a 16-bit offset.Instruction prefixes allow temporary overrides of the default address and/or operandsizes from within a program.When operating in protected mode, the segment descriptor for the currentlyexecuting code segment defines the default address and operand size.
A segmentdescriptor is a system data structure not normally visible to application code. Assembler directives allow the default addressing and operand size to be chosen for aprogram. The assembler and other tools then set up the segment descriptor for thecode segment appropriately.When operating in real-address mode, the default addressing and operand size is 16bits. An address-size override can be used in real-address mode to enable 32-bitaddressing.
However, the maximum allowable 32-bit linear address is still 000FFFFFH(220-1).Vol. 1 3-11BASIC EXECUTION ENVIRONMENT3.3.6Extended Physical Addressing in Protected ModeBeginning with P6 family processors, the IA-32 architecture supports addressing ofup to 64 GBytes (236 bytes) of physical memory. A program or task could notaddress locations in this address space directly. Instead, it addresses individual linearaddress spaces of up to 4 GBytes that mapped to 64-GByte physical address spacethrough a virtual memory management mechanism.
Using this mechanism, an operating system can enable a program to switch 4-GByte linear address spaces within64-GByte physical address space.The use of extended physical addressing requires the processor to operate inprotected mode and the operating system to provide a virtual memory managementsystem. See “36-Bit Physical Addressing Using the PAE Paging Mechanism” inChapter 3, “Protected-Mode Memory Management,” of the Intel® 64 and IA-32Architectures Software Developer’s Manual, Volume 3A.3.3.7Address Calculations in 64-Bit ModeIn most cases, 64-bit mode uses flat address space for code, data, and stacks. In64-bit mode (if there is no address-size override), the size of effective address calculations is 64 bits. An effective-address calculation uses a 64-bit base and index registers and sign-extend displacements to 64 bits.In the flat address space of 64-bit mode, linear addresses are equal to effectiveaddresses because the base address is zero.
In the event that FS or GS segments areused with a non-zero base, this rule does not hold. In 64-bit mode, the effectiveaddress components are added and the effective address is truncated (See forexample the instruction LEA) before adding the full 64-bit segment base.
The base isnever truncated, regardless of addressing mode in 64-bit mode.The instruction pointer is extended to 64 bits to support 64-bit code offsets. The64-bit instruction pointer is called the RIP. Table 3-1 shows the relationship betweenRIP, EIP, and IP.Table 3-1. Instruction Pointer SizesBits 63:3216-bit instruction pointerBits 31:16Not Modified32-bit instruction pointerZero Extension64-bit instruction pointerRIPBits 15:0IPEIPGenerally, displacements and immediates in 64-bit mode are not extended to 64 bits.They are still limited to 32 bits and sign-extended during effective-address calculations. In 64-bit mode, however, support is provided for 64-bit displacement andimmediate forms of the MOV instruction.All 16-bit and 32-bit address calculations are zero-extended in IA-32e mode to form64-bit addresses.
Address calculations are first truncated to the effective address3-12 Vol. 1BASIC EXECUTION ENVIRONMENTsize of the current mode (64-bit mode or compatibility mode), as overridden by anyaddress-size prefix. The result is then zero-extended to the full 64-bit address width.Because of this, 16-bit and 32-bit applications running in compatibility mode canaccess only the low 4 GBytes of the 64-bit mode effective addresses.
Likewise, a32-bit address generated in 64-bit mode can access only the low 4 GBytes of the64-bit mode effective addresses.3.3.7.1Canonical AddressingIn 64-bit mode, an address is considered to be in canonical form if address bits 63through to the most-significant implemented bit by the microarchitecture are set toeither all ones or all zeros.Intel 64 architecture defines a 64-bit linear address. Implementations can supportless.
The first implementation of IA-32 processors with Intel 64 architecture supportsa 48-bit linear address. This means a canonical address must have bits 63 through 48set to zeros or ones (depending on whether bit 47 is a zero or one).Although implementations may not use all 64 bits of the linear address, they shouldcheck bits 63 through the most-significant implemented bit to see if the address is incanonical form. If a linear-memory reference is not in canonical form, the implementation should generate an exception. In most cases, a general-protection exception(#GP) is generated. However, in the case of explicit or implied stack references, astack fault (#SS) is generated.Instructions that have implied stack references, by default, use the SS segmentregister. These include PUSH/POP-related instructions and instructions usingRSP/RBP as base registers.
In these cases, the canonical fault is #SF.If an instruction uses base registers RSP/RBP and uses a segment override prefix tospecify a non-SS segment, a canonical fault generates a #GP (instead of an #SF). In64-bit mode, only FS and GS segment-overrides are applicable in this situation.Other segment override prefixes (CS, DS, ES and SS) are ignored. Note that this alsomeans that an SS segment-override applied to a “non-stack” register reference isignored.
Such a sequence still produces a #GP for a canonical fault (and not an #SF).3.4BASIC PROGRAM EXECUTION REGISTERSIA-32 architecture provides 16 basic program execution registers for use in generalsystem and application programing (see Figure 3-4). These registers can be groupedas follows:•General-purpose registers. These eight registers are available for storingoperands and pointers.•Segment registers. These registers hold up to six segment selectors.Vol. 1 3-13BASIC EXECUTION ENVIRONMENT•EFLAGS (program status and control) register. The EFLAGS register reporton the status of the program being executed and allows limited (applicationprogram level) control of the processor.•EIP (instruction pointer) register.
The EIP register contains a 32-bit pointerto the next instruction to be executed.3.4.1General-Purpose RegistersThe 32-bit general-purpose registers EAX, EBX, ECX, EDX, ESI, EDI, EBP, and ESPare provided for holding the following items:•••Operands for logical and arithmetic operationsOperands for address calculationsMemory pointersAlthough all of these registers are available for general storage of operands, results,and pointers, caution should be used when referencing the ESP register. The ESPregister holds the stack pointer and as a general rule should not be used for anotherpurpose.Many instructions assign specific registers to hold operands. For example, stringinstructions use the contents of the ECX, ESI, and EDI registers as operands.
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