Volume 1 Basic Architecture (794100), страница 20
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See Chapter 18,“Debugging and Performance Monitoring,” in the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 3B.The remainder of this chapter describes the organization of memory and the addressspace, the basic program execution registers, and addressing modes. Refer to theVol. 1 3-5BASIC EXECUTION ENVIRONMENTfollowing chapters in this volume for descriptions of the other program executionresources shown in Figure 3-1:••x87 FPU registers — See Chapter 8, “Programming with the x87 FPU.”•XMM registers — See Chapter 10, “Programming with Streaming SIMDExtensions (SSE),” Chapter 11, “Programming with Streaming SIMD Extensions 2(SSE2),” and Chapter 12, “Programming with SSE3 and Supplemental SSE3.”•Stack implementation and procedure calls — See Chapter 6, “ProcedureCalls, Interrupts, and Exceptions.”MMX Registers — See Chapter 9, “Programming with Intel® MMX™Technology.”3.2.164-Bit Mode Execution EnvironmentThe execution environment for 64-bit mode is similar to that described in Section3.2.
The following paragraphs describe the differences that apply.•Address space — A task or program running in 64-bit mode on an IA-32processor can address linear address space of up to 264 bytes (subject to thecanonical addressing requirement described in Section 3.3.7.1) and physicaladdress space of up to 240 bytes. Software can query CPUID for the physicaladdress size supported by a processor.•Basic program execution registers — The number of general-purposeregisters (GPRs) available is 16. GPRs are 64-bits wide and they supportoperations on byte, word, doubleword and quadword integers.
Accessing byteregisters is done uniformly to the lowest 8 bits. The instruction pointer registerbecomes 64 bits. The EFLAGS register is extended to 64 bits wide, and is referredto as the RFLAGS register. The upper 32 bits of RFLAGS is reserved. The lower 32bits of RFLAGS is the same as EFLAGS. See Figure 3-2.•XMM registers — There are 16 XMM data registers for SIMD operations.
SeeSection 10.2, “SSE Programming Environment,” for more information aboutthese registers.•Stack — The stack pointer size is 64 bits. Stack size is not controlled by a bit inthe SS descriptor (as it is in non-64-bit modes) nor can the pointer size beoverridden by an instruction prefix.•Control registers — Control registers expand to 64 bits.
A new control register(the task priority register: CR8 or TPR) has been added. See Chapter 2, “Intel®64 and IA-32 Architectures,” in the Intel® 64 and IA-32 Architectures SoftwareDeveloper’s Manual, Volume 3A.•Debug registers — Debug registers expand to 64 bits. See Chapter 18,“Debugging and Performance Monitoring,” in the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 3B.•Descriptor table registers — The global descriptor table register (GDTR) andinterrupt descriptor table register (IDTR) expand to 10 bytes so that they can3-6 Vol.
1BASIC EXECUTION ENVIRONMENThold a full 64-bit base address. The local descriptor table register (LDTR) and thetask register (TR) also expand to hold a full 64-bit base address.Basic Program Execution RegistersAddress Space264 -1Sixteen 64-bitRegistersSix 16-bitRegistersGeneral-Purpose RegistersSegment Registers64-bitsRFLAGS Register64-bitsRIP (Instruction Pointer Register)FPU RegistersFloating-PointData RegistersEight 80-bitRegisters016 bitsControl Register16 bitsStatus Register16 bitsTag RegisterOpcode Register (11-bits)64 bitsFPU Instruction Pointer Register64 bitsFPU Data (Operand) Pointer RegisterMMX RegistersEight 64-bitRegistersMMX RegistersXMM RegistersSixteen 128-bitRegistersXMM Registers32-bitsMXCSR RegisterFigure 3-2. 64-Bit Mode Execution EnvironmentVol.
1 3-7BASIC EXECUTION ENVIRONMENT3.3MEMORY ORGANIZATIONThe memory that the processor addresses on its bus is called physical memory.Physical memory is organized as a sequence of 8-bit bytes. Each byte is assigned aunique address, called a physical address. The physical address space rangesfrom zero to a maximum of 236 − 1 (64 GBytes) if the processor does not supportIntel 64 architecture. Intel 64 architecture introduces a changes in physical andlinear address space; these are described in Section 3.3.3, Section 3.3.4, andSection 3.3.7.Virtually any operating system or executive designed to work with an IA-32 or Intel64 processor will use the processor’s memory management facilities to accessmemory.
These facilities provide features such as segmentation and paging, whichallow memory to be managed efficiently and reliably. Memory management isdescribed in detail in Chapter 3, “Protected-Mode Memory Management,” in theIntel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 3A. Thefollowing paragraphs describe the basic methods of addressing memory whenmemory management is used.3.3.1IA-32 Memory ModelsWhen employing the processor’s memory management facilities, programs do notdirectly address physical memory. Instead, they access memory using one of threememory models: flat, segmented, or real address mode:•Flat memory model — Memory appears to a program as a single, continuousaddress space (Figure 3-3).
This space is called a linear address space. Code,data, and stacks are all contained in this address space. Linear address space isbyte addressable, with addresses running contiguously from 0 to 232 - 1 (if not in64-bit mode). An address for any byte in linear address space is called a linearaddress.•Segmented memory model — Memory appears to a program as a group ofindependent address spaces called segments. Code, data, and stacks aretypically contained in separate segments. To address a byte in a segment, aprogram issues a logical address. This consists of a segment selector and anoffset (logical addresses are often referred to as far pointers).
The segmentselector identifies the segment to be accessed and the offset identifies a byte inthe address space of the segment. Programs running on an IA-32 processor canaddress up to 16,383 segments of different sizes and types, and each segmentcan be as large as 232 bytes.Internally, all the segments that are defined for a system are mapped into theprocessor’s linear address space. To access a memory location, the processorthus translates each logical address into a linear address. This translation istransparent to the application program.The primary reason for using segmented memory is to increase the reliability ofprograms and systems. For example, placing a program’s stack in a separate3-8 Vol.
1BASIC EXECUTION ENVIRONMENTsegment prevents the stack from growing into the code or data space andoverwriting instructions or data, respectively.•Real-address mode memory model — This is the memory model for the Intel8086 processor. It is supported to provide compatibility with existing programswritten to run on the Intel 8086 processor. The real-address mode uses a specificimplementation of segmented memory in which the linear address space for theprogram and the operating system/executive consists of an array of segments ofup to 64 KBytes in size each. The maximum size of the linear address space inreal-address mode is 220 bytes.See also: Chapter 15, “8086 Emulation,” Intel® 64 and IA-32 ArchitecturesSoftware Developer’s Manual, Volume 3A.Flat ModelLinear AddressLinearAddressSpace*Segmented ModelSegmentsLinearAddressSpace*Offset (effective address)LogicalAddress Segment SelectorReal-Address Mode ModelOffsetLogicalAddress Segment SelectorLinear AddressSpace DividedInto EqualSized Segments* The linear address spacecan be paged when using theflat or segmented model.Figure 3-3.
Three Memory Management ModelsVol. 1 3-9BASIC EXECUTION ENVIRONMENT3.3.2Paging and Virtual MemoryWith the flat or the segmented memory model, linear address space is mapped intothe processor’s physical address space either directly or through paging. When usingdirect mapping (paging disabled), each linear address has a one-to-one correspondence with a physical address. Linear addresses are sent out on the processor’saddress lines without translation.When using the IA-32 architecture’s paging mechanism (paging enabled), linearaddress space is divided into pages which are mapped to virtual memory.
The pagesof virtual memory are then mapped as needed into physical memory. When an operating system or executive uses paging, the paging mechanism is transparent to anapplication program. All that the application sees is linear address space.In addition, IA-32 architecture’s paging mechanism includes extensions thatsupport:•Page Address Extensions (PAE) to address physical address space greater than4 GBytes.•Page Size Extensions (PSE) to map linear address to physical address in4-MBytes pages.See also: Chapter 3, “Protected-Mode Memory Management,” in the Intel® 64 andIA-32 Architectures Software Developer’s Manual, Volume 3A.3.3.3Memory Organization in 64-Bit ModeIntel 64 architecture supports physical address space greater than 64 GBytes; theactual physical address size of IA-32 processors is implementation specific.
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