Volume 1 Basic Architecture (794100), страница 33

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1 5-9INSTRUCTION SET SUMMARYUD2Undefined instructionXLAT/XLATBTable lookup translationCPUIDProcessor Identification5.2X87 FPU INSTRUCTIONSThe x87 FPU instructions are executed by the processor’s x87 FPU. These instructionsoperate on floating-point, integer, and binary-coded decimal (BCD) operands. Formore detail on x87 FPU instructions, see Chapter 8, “Programming with the x87 FPU.”These instructions are divided into the following subgroups: data transfer, loadconstants, and FPU control instructions. The sections that follow introduce eachsubgroup.5.2.1x87 FPU Data Transfer InstructionsThe data transfer instructions move floating-point, integer, and BCD values betweenmemory and the x87 FPU registers. They also perform conditional move operationson floating-point operands.FLDLoad floating-point valueFSTStore floating-point valueFSTPStore floating-point value and popFILDLoad integerFISTStore integerFISTP1Store integer and popFBLDLoad BCDFBSTPStore BCD and popFXCHExchange registersFCMOVEFloating-point conditional move if equalFCMOVNEFloating-point conditional move if not equalFCMOVBFloating-point conditional move if belowFCMOVBEFloating-point conditional move if below or equalFCMOVNBFloating-point conditional move if not belowFCMOVNBEFloating-point conditional move if not below or equalFCMOVUFloating-point conditional move if unorderedFCMOVNUFloating-point conditional move if not unordered1.

SSE3 provides an instruction FISTTP for integer conversion.5-10 Vol. 1INSTRUCTION SET SUMMARY5.2.2x87 FPU Basic Arithmetic InstructionsThe basic arithmetic instructions perform basic arithmetic operations on floatingpoint and integer operands.FADDAdd floating-pointFADDPAdd floating-point and popFIADDAdd integerFSUBSubtract floating-pointFSUBPSubtract floating-point and popFISUBSubtract integerFSUBRSubtract floating-point reverseFSUBRPSubtract floating-point reverse and popFISUBRSubtract integer reverseFMULMultiply floating-pointFMULPMultiply floating-point and popFIMULMultiply integerFDIVDivide floating-pointFDIVPDivide floating-point and popFIDIVDivide integerFDIVRDivide floating-point reverseFDIVRPDivide floating-point reverse and popFIDIVRDivide integer reverseFPREMPartial remainderFPREM1IEEE Partial remainderFABSAbsolute valueFCHSChange signFRNDINTRound to integerFSCALEScale by power of twoFSQRTSquare rootFXTRACTExtract exponent and significand5.2.3x87 FPU Comparison InstructionsThe compare instructions examine or compare floating-point or integer operands.FCOMCompare floating-pointFCOMPCompare floating-point and popFCOMPPCompare floating-point and pop twiceFUCOMUnordered compare floating-pointVol.

1 5-11INSTRUCTION SET SUMMARYFUCOMPUnordered compare floating-point and popFUCOMPPUnordered compare floating-point and pop twiceFICOMCompare integerFICOMPCompare integer and popFCOMICompare floating-point and set EFLAGSFUCOMIUnordered compare floating-point and set EFLAGSFCOMIPCompare floating-point, set EFLAGS, and popFUCOMIPUnordered compare floating-point, set EFLAGS, and popFTSTTest floating-point (compare with 0.0)FXAMExamine floating-point5.2.4x87 FPU Transcendental InstructionsThe transcendental instructions perform basic trigonometric and logarithmic operations on floating-point operands.FSINSineFCOSCosineFSINCOSSine and cosineFPTANPartial tangentFPATANPartial arctangentF2XM12x − 1FYL2Xy∗log2xFYL2XP1y∗log2(x+1)5.2.5x87 FPU Load Constants InstructionsThe load constants instructions load common constants, such as π, into the x87floating-point registers.FLD1Load +1.0FLDZLoad +0.0FLDPILoad πFLDL2ELoad log2eFLDLN2Load loge2FLDL2TLoad log210FLDLG2Load log1025-12 Vol.

1INSTRUCTION SET SUMMARY5.2.6x87 FPU Control InstructionsThe x87 FPU control instructions operate on the x87 FPU register stack and save andrestore the x87 FPU state.FINCSTPFDECSTPFFREEFINITFNINITFCLEXFNCLEXFSTCWFNSTCWFLDCWFSTENVFNSTENVFLDENVFSAVEFNSAVEFRSTORFSTSWFNSTSWWAIT/FWAITFNOP5.3Increment FPU register stack pointerDecrement FPU register stack pointerFree floating-point registerInitialize FPU after checking error conditionsInitialize FPU without checking error conditionsClear floating-point exception flags after checking for errorconditionsClear floating-point exception flags without checking for errorconditionsStore FPU control word after checking error conditionsStore FPU control word without checking error conditionsLoad FPU control wordStore FPU environment after checking error conditionsStore FPU environment without checking error conditionsLoad FPU environmentSave FPU state after checking error conditionsSave FPU state without checking error conditionsRestore FPU stateStore FPU status word after checking error conditionsStore FPU status word without checking error conditionsWait for FPUFPU no operationX87 FPU AND SIMD STATE MANAGEMENTINSTRUCTIONSTwo state management instructions were introduced into the IA-32 architecture withthe Pentium II processor family:FXSAVEFXRSTORSave x87 FPU and SIMD stateRestore x87 FPU and SIMD stateInitially, these instructions operated only on the x87 FPU (and MMX) registers toperform a fast save and restore, respectively, of the x87 FPU and MMX state.

With theintroduction of SSE extensions in the Pentium III processor family, these instructionswere expanded to also save and restore the state of the XMM and MXCSR registers.Intel 64 architecture also supports these instructions.See Section 10.5, “FXSAVE and FXRSTOR Instructions,” for more detail.Vol. 1 5-13INSTRUCTION SET SUMMARY5.4MMX™ INSTRUCTIONSFour extensions have been introduced into the IA-32 architecture to permit IA-32processors to perform single-instruction multiple-data (SIMD) operations. Theseextensions include the MMX technology, SSE extensions, SSE2 extensions, and SSE3extensions. For a discussion that puts SIMD instructions in their historical context,see Section 2.2.4, “SIMD Instructions.”MMX instructions operate on packed byte, word, doubleword, or quadword integeroperands contained in memory, in MMX registers, and/or in general-purpose registers.

For more detail on these instructions, see Chapter 9, “Programming with Intel®MMX™ Technology.”MMX instructions can only be executed on Intel 64 and IA-32 processors that supportthe MMX technology. Support for these instructions can be detected with the CPUIDinstruction. See the description of the CPUID instruction in Chapter 3, “InstructionSet Reference, A-M,” of the Intel® 64 and IA-32 Architectures Software Developer’sManual, Volume 2A.MMX instructions are divided into the following subgroups: data transfer, conversion,packed arithmetic, comparison, logical, shift and rotate, and state managementinstructions. The sections that follow introduce each subgroup.5.4.1MMX Data Transfer InstructionsThe data transfer instructions move doubleword and quadword operands betweenMMX registers and between MMX registers and memory.MOVDMOVQMove doublewordMove quadword5.4.2MMX Conversion InstructionsThe conversion instructions pack and unpack bytes, words, and doublewordsPACKSSWBPack words into bytes with signed saturationPACKSSDWPack doublewords into words with signed saturationPACKUSWBPack words into bytes with unsigned saturation.PUNPCKHBWUnpack high-order bytesPUNPCKHWDUnpack high-order wordsPUNPCKHDQUnpack high-order doublewordsPUNPCKLBWUnpack low-order bytesPUNPCKLWDUnpack low-order wordsPUNPCKLDQUnpack low-order doublewords5-14 Vol.

1INSTRUCTION SET SUMMARY5.4.3MMX Packed Arithmetic InstructionsThe packed arithmetic instructions perform packed integer arithmetic on packedbyte, word, and doubleword integers.PADDBPADDWPADDDPADDSBPADDSWPADDUSBPADDUSWPSUBBPSUBWPSUBDPSUBSBPSUBSWPSUBUSBPSUBUSWPMULHWPMULLWPMADDWD5.4.4Add packed byte integersAdd packed word integersAdd packed doubleword integersAdd packed signed byte integers with signed saturationAdd packed signed word integers with signed saturationAdd packed unsigned byte integers with unsigned saturationAdd packed unsigned word integers with unsigned saturationSubtract packed byte integersSubtract packed word integersSubtract packed doubleword integersSubtract packed signed byte integers with signed saturationSubtract packed signed word integers with signed saturationSubtract packed unsigned byte integers with unsigned saturationSubtract packed unsigned word integers with unsignedsaturationMultiply packed signed word integers and store high resultMultiply packed signed word integers and store low resultMultiply and add packed word integersMMX Comparison InstructionsThe compare instructions compare packed bytes, words, or doublewords.PCMPEQBPCMPEQWPCMPEQDPCMPGTBPCMPGTWPCMPGTD5.4.5CompareCompareCompareCompareCompareComparepackedpackedpackedpackedpackedpackedbytes for equalwords for equaldoublewords for equalsigned byte integers for greater thansigned word integers for greater thansigned doubleword integers for greater thanMMX Logical InstructionsThe logical instructions perform AND, AND NOT, OR, and XOR operations on quadword operands.PANDPANDNPORPXORBitwiseBitwiseBitwiseBitwiselogicallogicallogicallogicalANDAND NOTORexclusive ORVol.

1 5-15INSTRUCTION SET SUMMARY5.4.6MMX Shift and Rotate InstructionsThe shift and rotate instructions shift and rotate packed bytes, words, or doublewords, or quadwords in 64-bit operands.PSLLWShift packed words left logicalPSLLDShift packed doublewords left logicalPSLLQShift packed quadword left logicalPSRLWShift packed words right logicalPSRLDShift packed doublewords right logicalPSRLQShift packed quadword right logicalPSRAWShift packed words right arithmeticPSRADShift packed doublewords right arithmetic5.4.7MMX State Management InstructionsThe EMMS instruction clears the MMX state from the MMX registers.EMMS5.5Empty MMX stateSSE INSTRUCTIONSSSE instructions represent an extension of the SIMD execution model introducedwith the MMX technology.

For more detail on these instructions, see Chapter 10,“Programming with Streaming SIMD Extensions (SSE).”SSE instructions can only be executed on Intel 64 and IA-32 processors that supportSSE extensions. Support for these instructions can be detected with the CPUIDinstruction. See the description of the CPUID instruction in Chapter 3, “InstructionSet Reference, A-M,” of the Intel® 64 and IA-32 Architectures Software Developer’sManual, Volume 2A.SSE instructions are divided into four subgroups (note that the first subgroup hassubordinate subgroups of its own):•SIMD single-precision floating-point instructions that operate on the XMMregisters•••MXSCR state management instructions64-bit SIMD integer instructions that operate on the MMX registersCacheability control, prefetch, and instruction ordering instructionsThe following sections provide an overview of these groups.5-16 Vol.

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