Volume 1 Basic Architecture (794100), страница 36
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See the description of the CPUID instruction in Chapter 3,“Instruction Set Reference, A-M,” of the Intel® 64 and IA-32 Architectures SoftwareDeveloper’s Manual, Volume 2A.The sections that follow describe each subgroup.Vol. 1 5-27INSTRUCTION SET SUMMARY5.8.1Horizontal Addition/SubtractionPHADDWAdds two adjacent, signed 16-bit integers horizontally from thesource and destination operands and packs the signed 16-bitresults to the destination operand.PHADDSWAdds two adjacent, signed 16-bit integers horizontally from thesource and destination operands and packs the signed, saturated 16-bit results to the destination operand.PHADDDAdds two adjacent, signed 32-bit integers horizontally from thesource and destination operands and packs the signed 32-bitresults to the destination operand.PHSUBWPerforms horizontal subtraction on each adjacent pair of 16-bitsigned integers by subtracting the most significant word fromthe least significant word of each pair in the source and destination operands.
The signed 16-bit results are packed and writtento the destination operand.PHSUBSWPerforms horizontal subtraction on each adjacent pair of 16-bitsigned integers by subtracting the most significant word fromthe least significant word of each pair in the source and destination operands. The signed, saturated 16-bit results are packedand written to the destination operand.PHSUBDPerforms horizontal subtraction on each adjacent pair of 32-bitsigned integers by subtracting the most significant doublewordfrom the least significant double word of each pair in the sourceand destination operands.
The signed 32-bit results are packedand written to the destination operand.5.8.2Packed Absolute ValuesPABSBComputes the absolute value of each signed byte data element.PABSWComputes the absolute value of each signed 16-bit dataelement.PABSDComputes the absolute value of each signed 32-bit dataelement.5.8.3Multiply and Add Packed Signed and Unsigned BytesPMADDUBSW5-28 Vol. 1Multiplies each unsigned byte value with the correspondingsigned byte value to produce an intermediate, 16-bit signedinteger. Each adjacent pair of 16-bit signed values are addedhorizontally.
The signed, saturated 16-bit results are packed tothe destination operand.INSTRUCTION SET SUMMARY5.8.4Packed Multiply High with Round and ScalePMULHRSW5.8.5Multiplies vertically each signed 16-bit integer from the destination operand with the corresponding signed 16-bit integer of thesource operand, producing intermediate, signed 32-bit integers.Each intermediate 32-bit integer is truncated to the 18 mostsignificant bits. Rounding is always performed by adding 1 to theleast significant bit of the 18-bit intermediate result. The finalresult is obtained by selecting the 16 bits immediately to theright of the most significant bit of each 18-bit intermediateresult and packed to the destination operand.Packed Shuffle BytesPSHUFB5.8.6Permutes each byte in place, according to a shuffle controlmask.
The least significant three or four bits of each shufflecontrol byte of the control mask form the shuffle index. Theshuffle mask is unaffected. If the most significant bit (bit 7) of ashuffle control byte is set, the constant zero is written in theresult byte.Packed SignPSIGNB/W/D5.8.7PALIGNR5.9Negates each signed integer element of the destination operandif the sign of the corresponding data element in the sourceoperand is less than zero.Packed Align RightSource operand is appended after the destination operandforming an intermediate value of twice the width of an operand.The result is extracted from the intermediate value into thedestination operand by selecting the 128 bit or 64 bit value thatare right-aligned to the byte offset specified by the immediatevalue.SYSTEM INSTRUCTIONSThe following system instructions are used to control those functions of the processorthat are provided to support for operating systems and executives.LGDTLoad global descriptor table (GDT) registerSGDTStore global descriptor table (GDT) registerLLDTLoad local descriptor table (LDT) registerVol.
1 5-29INSTRUCTION SET SUMMARYSLDTStore local descriptor table (LDT) registerLTRLoad task registerSTRStore task registerLIDTLoad interrupt descriptor table (IDT) registerSIDTStore interrupt descriptor table (IDT) registerMOVLoad and store control registersLMSWLoad machine status wordSMSWStore machine status wordCLTSClear the task-switched flagARPLAdjust requested privilege levelLARLoad access rightsLSLLoad segment limitVERRVerify segment for readingVERWVerify segment for writingMOVLoad and store debug registersINVDInvalidate cache, no writebackWBINVDInvalidate cache, with writebackINVLPGInvalidate TLB EntryLOCK (prefix)Lock BusHLTHalt processorRSMReturn from system management mode (SMM)RDMSRRead model-specific registerWRMSRWrite model-specific registerRDPMCRead performance monitoring countersRDTSCRead time stamp counterSYSENTERFast System Call, transfers to a flat protected mode kernel atCPL = 0SYSEXITFast System Call, transfers to a flat protected mode kernel atCPL = 35.1064-BIT MODE INSTRUCTIONSThe following instructions are introduced in 64-bit mode.
This mode is a sub-mode ofIA-32e mode.CDQEConvert doubleword to quadwordCMPSQCompare string operandsCMPXCHG16BCompare RDX:RAX with m128LODSQLoad qword at address (R)SI into RAX5-30 Vol. 1INSTRUCTION SET SUMMARYMOVSQMove qword from address (R)SI to (R)DIMOVZX (64-bits)Move doubleword to quadword, zero-extensionSTOSQStore RAX at address RDISWAPGSExchanges current GS base register value with value in MSRaddress C0000102HSYSCALLFast call to privilege level 0 system proceduresSYSRETReturn from fast system call5.11VIRTUAL-MACHINE EXTENSIONSThe behavior of the VMCS-maintenance instructions is summarized below:VMPTRLDTakes a single 64-bit source operand in memory. It makes thereferenced VMCS active and current.VMPTRSTTakes a single 64-bit destination operand that is in memory.Current-VMCS pointer is stored into the destination operand.VMCLEARTakes a single 64-bit operand in memory.
The instruction setsthe launch state of the VMCS referenced by the operand to“clear”, renders that VMCS inactive, and ensures that data forthe VMCS have been written to the VMCS-data area in the referenced VMCS region.VMREADReads a component from the VMCS (the encoding of that field isgiven in a register operand) and stores it into a destinationoperand.VMWRITEWrites a component to the VMCS (the encoding of that field isgiven in a register operand) from a source operand.The behavior of the VMX management instructions is summarized below:VMCALLAllows a guest in VMX non-root operation to call the VMM forservice.
A VM exit occurs, transferring control to the VMM.VMLAUNCHLaunches a virtual machine managed by the VMCS. A VM entryoccurs, transferring control to the VM.VMRESUMEResumes a virtual machine managed by the VMCS. A VM entryoccurs, transferring control to the VM.VMXOFFCauses the processor to leave VMX operation.VMXONTakes a single 64-bit source operand in memory. It causes alogical processor to enter VMX root operation and to use thememory referenced by the operand to support VMX operation.Vol. 1 5-31INSTRUCTION SET SUMMARY5-32 Vol.
1CHAPTER 6PROCEDURE CALLS, INTERRUPTS, AND EXCEPTIONSThis chapter describes the facilities in the Intel 64 and IA-32 architectures forexecuting calls to procedures or subroutines. It also describes how interrupts andexceptions are handled from the perspective of an application programmer.6.1PROCEDURE CALL TYPESThe processor supports procedure calls in the following two different ways:••CALL and RET instructions.ENTER and LEAVE instructions, in conjunction with the CALL and RETinstructions.Both of these procedure call mechanisms use the procedure stack, commonlyreferred to simply as “the stack,” to save the state of the calling procedure, passparameters to the called procedure, and store local variables for the currentlyexecuting procedure.The processor’s facilities for handling interrupts and exceptions are similar to thoseused by the CALL and RET instructions.6.2STACKSThe stack (see Figure 6-1) is a contiguous array of memory locations.
It is containedin a segment and identified by the segment selector in the SS register. When usingthe flat memory model, the stack can be located anywhere in the linear addressspace for the program. A stack can be up to 4 GBytes long, the maximum size of asegment.Items are placed on the stack using the PUSH instruction and removed from thestack using the POP instruction. When an item is pushed onto the stack, theprocessor decrements the ESP register, then writes the item at the new top of stack.When an item is popped off the stack, the processor reads the item from the top ofstack, then increments the ESP register. In this manner, the stack grows down inmemory (towards lesser addresses) when items are pushed on the stack and shrinksup (towards greater addresses) when the items are popped from the stack.A program or operating system/executive can set up many stacks.
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