Volume 1 Basic Architecture (794100), страница 40
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If an interruptor exception handler is called through an interrupt gate, the processor clears theinterrupt enable (IF) flag in the EFLAGS register to prevent subsequent interruptsfrom interfering with the execution of the handler. When a handler is called througha trap gate, the state of the IF flag is not changed.Table 6-1. Exceptions and InterruptsVector No. MnemonicDescriptionSource0#DEDivide ErrorDIV and IDIV instructions.1#DBDebugAny code or data reference.NMI InterruptNon-maskable external interrupt.23#BPBreakpointINT 3 instruction.4#OFOverflowINTO instruction.5#BRBOUND Range ExceededBOUND instruction.6#UDInvalid Opcode (UnDefinedOpcode)UD2 instruction or reserved opcode.17#NMDevice Not Available (No MathCoprocessor)Floating-point or WAIT/FWAITinstruction.8#DFDouble FaultAny instruction that can generate anexception, an NMI, or an INTR.9#MFCoProcessor Segment Overrun(reserved)Floating-point instruction.210#TSInvalid TSSTask switch or TSS access.11#NPSegment Not PresentLoading segment registers or accessingsystem segments.12#SSStack Segment FaultStack operations and SS register loads.13#GPGeneral ProtectionAny memory reference and otherprotection checks.6-14 Vol.
2PROCEDURE CALLS, INTERRUPTS, AND EXCEPTIONSTable 6-1. Exceptions and Interrupts (Contd.)Vector No. Mnemonic14#PF15DescriptionPage FaultSourceAny memory reference.Reserved16#MFFloating-Point Error (MathFault)Floating-point or WAIT/FWAITinstruction.17#ACAlignment CheckAny data reference in memory.318#MCMachine CheckError codes (if any) and source are modeldependent.419#XMSIMD Floating-Point ExceptionSIMD Floating-Point Instruction520-31Reserved32-255Maskable InterruptsExternal interrupt from INTR pin or INT ninstruction.NOTES:1. The UD2 instruction was introduced in the Pentium Pro processor.2. IA-32 processors after the Intel386 processor do not generate this exception.3.
This exception was introduced in the Intel486 processor.4. This exception was introduced in the Pentium processor and enhanced in the P6 family processors.5. This exception was introduced in the Pentium III processor.If the code segment for the handler procedure has the same privilege level as thecurrently executing program or task, the handler procedure uses the current stack; ifthe handler executes at a more privileged level, the processor switches to the stackfor the handler’s privilege level.If no stack switch occurs, the processor does the following when calling an interruptor exception handler (see Figure 6-5):1.
Pushes the current contents of the EFLAGS, CS, and EIP registers (in that order)on the stack.2. Pushes an error code (if appropriate) on the stack.3. Loads the segment selector for the new code segment and the new instructionpointer (from the interrupt gate or trap gate) into the CS and EIP registers,respectively.4. If the call is through an interrupt gate, clears the IF flag in the EFLAGS register.5. Begins execution of the handler procedure.Vol. 2 6-15PROCEDURE CALLS, INTERRUPTS, AND EXCEPTIONSInterrupted Procedure’sand Handler’s StackEFLAGSCSEIPError CodeStack Usage with NoPrivilege-Level ChangeESP BeforeTransfer to HandlerESP AfterTransfer to HandlerStack Usage withPrivilege-Level ChangeInterrupted Procedure’sStackHandler’s StackESP BeforeTransfer to HandlerESP AfterTransfer to HandlerSSESPEFLAGSCSEIPError CodeFigure 6-5.
Stack Usage on Transfers to Interrupt and Exception Handling RoutinesIf a stack switch does occur, the processor does the following:1. Temporarily saves (internally) the current contents of the SS, ESP, EFLAGS, CS,and EIP registers.2. Loads the segment selector and stack pointer for the new stack (that is, the stackfor the privilege level being called) from the TSS into the SS and ESP registersand switches to the new stack.3. Pushes the temporarily saved SS, ESP, EFLAGS, CS, and EIP values for theinterrupted procedure’s stack onto the new stack.4. Pushes an error code on the new stack (if appropriate).5.
Loads the segment selector for the new code segment and the new instructionpointer (from the interrupt gate or trap gate) into the CS and EIP registers,respectively.6. If the call is through an interrupt gate, clears the IF flag in the EFLAGS register.7. Begins execution of the handler procedure at the new privilege level.6-16 Vol. 2PROCEDURE CALLS, INTERRUPTS, AND EXCEPTIONSA return from an interrupt or exception handler is initiated with the IRET instruction.The IRET instruction is similar to the far RET instruction, except that it also restoresthe contents of the EFLAGS register for the interrupted procedure. When executing areturn from an interrupt or exception handler from the same privilege level as theinterrupted procedure, the processor performs these actions:1. Restores the CS and EIP registers to their values prior to the interrupt orexception.2.
Restores the EFLAGS register.3. Increments the stack pointer appropriately.4. Resumes execution of the interrupted procedure.When executing a return from an interrupt or exception handler from a different privilege level than the interrupted procedure, the processor performs these actions:1.
Performs a privilege check.2. Restores the CS and EIP registers to their values prior to the interrupt orexception.3. Restores the EFLAGS register.4. Restores the SS and ESP registers to their values prior to the interrupt orexception, resulting in a stack switch back to the stack of the interruptedprocedure.5. Resumes execution of the interrupted procedure.6.4.2Calls to Interrupt or Exception Handler TasksInterrupt and exception handler routines can also be executed in a separate task.Here, an interrupt or exception causes a task switch to a handler task. The handlertask is given its own address space and (optionally) can execute at a higher protection level than application programs or tasks.The switch to the handler task is accomplished with an implicit task call that references a task gate descriptor.
The task gate provides access to the address spacefor the handler task. As part of the task switch, the processor saves complete stateinformation for the interrupted program or task. Upon returning from the handlertask, the state of the interrupted program or task is restored and executioncontinues.
See Chapter 5, “Interrupt and Exception Handling,” in the Intel® 64 andIA-32 Architectures Software Developer’s Manual, Volume 3B, for more informationon handling interrupts and exceptions through handler tasks.6.4.3Interrupt and Exception Handling in Real-Address ModeWhen operating in real-address mode, the processor responds to an interrupt orexception with an implicit far call to an interrupt or exception handler. The processoruses the interrupt or exception vector number as an index into an interrupt table. TheVol. 2 6-17PROCEDURE CALLS, INTERRUPTS, AND EXCEPTIONSinterrupt table contains instruction pointers to the interrupt and exception handlerprocedures.The processor saves the state of the EFLAGS register, the EIP register, the CSregister, and an optional error code on the stack before switching to the handlerprocedure.A return from the interrupt or exception handler is carried out with the IRETinstruction.See Chapter 15, “8086 Emulation,” in the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 3A, for more information on handling interruptsand exceptions in real-address mode.6.4.4INT n, INTO, INT 3, and BOUND InstructionsThe INT n, INTO, INT 3, and BOUND instructions allow a program or task to explicitlycall an interrupt or exception handler.
The INT n instruction uses an interrupt vectoras an argument, which allows a program to call any interrupt handler.The INTO instruction explicitly calls the overflow exception (#OF) handler if the overflow flag (OF) in the EFLAGS register is set. The OF flag indicates overflow on arithmetic instructions, but it does not automatically raise an overflow exception. Anoverflow exception can only be raised explicitly in either of the following ways:••Execute the INTO instruction.Test the OF flag and execute the INT n instruction with an argument of 4 (thevector number of the overflow exception) if the flag is set.Both the methods of dealing with overflow conditions allow a program to test foroverflow at specific places in the instruction stream.The INT 3 instruction explicitly calls the breakpoint exception (#BP) handler.The BOUND instruction explicitly calls the BOUND-range exceeded exception (#BR)handler if an operand is found to be not within predefined boundaries in memory.This instruction is provided for checking references to arrays and other data structures.
Like the overflow exception, the BOUND-range exceeded exception can onlybe raised explicitly with the BOUND instruction or the INT n instruction with an argument of 5 (the vector number of the bounds-check exception). The processor doesnot implicitly perform bounds checks and raise the BOUND-range exceeded exception.6.4.5Handling Floating-Point ExceptionsWhen operating on individual or packed floating-point values, the IA-32 architecturesupports a set of six floating-point exceptions.
These exceptions can be generatedduring operations performed by the x87 FPU instructions or by SSE/SSE2/SSE3instructions. When an x87 FPU instruction (including the FISTTP instruction in SSE3)generates one or more of these exceptions, it in turn generates floating-point error6-18 Vol. 2PROCEDURE CALLS, INTERRUPTS, AND EXCEPTIONSexception (#MF); when an SSE/SSE2/SSE3 instruction generates a floating-pointexception, it in turn generates SIMD floating-point exception (#XM).See the following sections for further descriptions of the floating-point exceptions,how they are generated, and how they are handled:•Section 4.9.1, “Floating-Point Exception Conditions,” and Section 4.9.3, “TypicalActions of a Floating-Point Exception Handler”•Section 8.4, “x87 FPU Floating-Point Exception Handling,” and Section 8.5, “x87FPU Floating-Point Exception Conditions”••Section 11.5.1, “SIMD Floating-Point Exceptions”Interrupt Behavior6.4.6Interrupt and Exception Behavior in 64-Bit Mode64-bit extensions expand the legacy IA-32 interrupt-processing and exceptionprocessing mechanism to allow support for 64-bit operating systems and applications.
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