Volume 1 Basic Architecture (794100), страница 39
Текст из файла (страница 39)
Pushes the temporarily saved SS and ESP values for the calling procedure’s stackonto the new stack.5. Copies the parameters from the calling procedure’s stack to the new stack. Avalue in the call gate descriptor determines how many parameters to copy to thenew stack.6. Pushes the temporarily saved CS and EIP values for the calling procedure to thenew stack.7.
Loads the segment selector for the new code segment and the new instructionpointer from the call gate into the CS and EIP registers, respectively.8. Begins execution of the called procedure at the new privilege level.When executing a return from the privileged procedure, the processor performsthese actions:1. Performs a privilege check.2. Restores the CS and EIP registers to their values prior to the call.3.
If the RET instruction has an optional n argument, increments the stack pointerby the number of bytes specified with the n operand to release parameters fromthe stack. If the call gate descriptor specifies that one or more parameters becopied from one stack to the other, a RET n instruction must be used to releasethe parameters from both stacks. Here, the n operand specifies the number ofbytes occupied on each stack by the parameters.
On a return, the processorincrements ESP by n for each stack to step over (effectively remove) theseparameters from the stacks.4. Restores the SS and ESP registers to their values prior to the call, which causes aswitch back to the stack of the calling procedure.5. If the RET instruction has an optional n argument, increments the stack pointerby the number of bytes specified with the n operand to release parameters fromthe stack (see explanation in step 3).6. Resumes execution of the calling procedure.See Chapter 4, “Protection,” in the Intel® 64 and IA-32 Architectures SoftwareDeveloper’s Manual, Volume 3A, for detailed information on calls to privileged levelsand the call gate descriptor.6.3.7Branch Functions in 64-Bit ModeThe 64-bit extensions expand branching mechanisms to accommodate branches in64-bit linear-address space.
These are:•Near-branch semantics are redefined in 64-bit modeVol. 2 6-11PROCEDURE CALLS, INTERRUPTS, AND EXCEPTIONS•In 64-bit mode and compatibility mode, 64-bit call-gate descriptors for far callsare availableIn 64-bit mode, the operand size for all near branches (CALL, RET, JCC, JCXZ, JMP,and LOOP) is forced to 64 bits. These instructions update the 64-bit RIP without theneed for a REX operand-size prefix.The following aspects of near branches are controlled by the effective operand size:••••Truncation of the size of the instruction pointerSize of a stack pop or push, due to a CALL or RETSize of a stack-pointer increment or decrement, due to a CALL or RETIndirect-branch operand sizeIn 64-bit mode, all of the above actions are forced to 64 bits regardless of operandsize prefixes (operand size prefixes are silently ignored). However, the displacementfield for relative branches is still limited to 32 bits and the address size for nearbranches is not forced in 64-bit mode.Address sizes affect the size of RCX used for JCXZ and LOOP; they also impact theaddress calculation for memory indirect branches.
Such addresses are 64 bits bydefault; but they can be overridden to 32 bits by an address size prefix.Software typically uses far branches to change privilege levels. The legacy IA-32architecture provides the call-gate mechanism to allow software to branch from oneprivilege level to another, although call gates can also be used for branches that donot change privilege levels. When call gates are used, the selector portion of thedirect or indirect pointer references a gate descriptor (the offset in the instruction isignored). The offset to the destination’s code segment is taken from the call-gatedescriptor.64-bit mode redefines the type value of a 32-bit call-gate descriptor type to a 64-bitcall gate descriptor and expands the size of the 64-bit descriptor to hold a 64-bitoffset.
The 64-bit mode call-gate descriptor allows far branches that reference anylocation in the supported linear-address space. These call gates also hold the targetcode selector (CS), allowing changes to privilege level and default size as a result ofthe gate transition.Because immediates are generally specified up to 32 bits, the only way to specify afull 64-bit absolute RIP in 64-bit mode is with an indirect branch.
For this reason,direct far branches are eliminated from the instruction set in 64-bit mode.64-bit mode also expands the semantics of the SYSENTER and SYSEXIT instructionsso that the instructions operate within a 64-bit memory space. The mode also introduces two new instructions: SYSCALL and SYSRET (which are valid only in 64-bitmode). For details, see “SYSENTER—Fast System Call” and “SYSEXIT—Fast Returnfrom Fast System Call” in Chapter 4, “Instruction Set Reference, N-Z,” of the Intel®64 and IA-32 Architectures Software Developer’s Manual, Volume 2B.6-12 Vol. 2PROCEDURE CALLS, INTERRUPTS, AND EXCEPTIONS6.4INTERRUPTS AND EXCEPTIONSThe processor provides two mechanisms for interrupting program execution, interrupts and exceptions:•An interrupt is an asynchronous event that is typically triggered by an I/Odevice.•An exception is a synchronous event that is generated when the processordetects one or more predefined conditions while executing an instruction.
TheIA-32 architecture specifies three classes of exceptions: faults, traps, and aborts.The processor responds to interrupts and exceptions in essentially the same way.When an interrupt or exception is signaled, the processor halts execution of thecurrent program or task and switches to a handler procedure that has been writtenspecifically to handle the interrupt or exception condition. The processor accessesthe handler procedure through an entry in the interrupt descriptor table (IDT). Whenthe handler has completed handling the interrupt or exception, program control isreturned to the interrupted program or task.The operating system, executive, and/or device drivers normally handle interruptsand exceptions independently from application programs or tasks. Applicationprograms can, however, access the interrupt and exception handlers incorporated inan operating system or executive through assembly-language calls.
The remainderof this section gives a brief overview of the processor’s interrupt and exceptionhandling mechanism. See Chapter 5, “Interrupt and Exception Handling,” in theIntel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 3B, for adescription of this mechanism.The IA-32 Architecture defines 18 predefined interrupts and exceptions and 224 userdefined interrupts, which are associated with entries in the IDT. Each interrupt andexception in the IDT is identified with a number, called a vector.
Table 6-1 lists theinterrupts and exceptions with entries in the IDT and their respective vectornumbers. Vectors 0 through 8, 10 through 14, and 16 through 19 are the predefinedinterrupts and exceptions, and vectors 32 through 255 are the user-defined interrupts, called maskable interrupts.Note that the processor defines several additional interrupts that do not point toentries in the IDT; the most notable of these interrupts is the SMI interrupt.
SeeChapter 5, “Interrupt and Exception Handling,” in the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 3B, for more information about theinterrupts and exceptions.When the processor detects an interrupt or exception, it does one of the followingthings:••Executes an implicit call to a handler procedure.Executes an implicit call to a handler task.Vol. 2 6-13PROCEDURE CALLS, INTERRUPTS, AND EXCEPTIONS6.4.1Call and Return Operation for Interrupt or ExceptionHandling ProceduresA call to an interrupt or exception handler procedure is similar to a procedure call toanother protection level (see Section 6.3.6, “CALL and RET Operation Between Privilege Levels”). Here, the interrupt vector references one of two kinds of gates: aninterrupt gate or a trap gate. Interrupt and trap gates are similar to call gates inthat they provide the following information:•••Access rights informationThe segment selector for the code segment that contains the handler procedureAn offset into the code segment to the first instruction of the handler procedureThe difference between an interrupt gate and a trap gate is as follows.
![](https://s.studizba.com/z.php?f=/templates/si/i/noavatar.png&w=100&h=100&t=1"){kind=avatar}
