Volume 1 Basic Architecture (794100), страница 31
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For example,the fraction 1/3 cannot be precisely represented in binary floating-point form. ThisVol. 1 4-29DATA TYPESexception occurs frequently and indicates that some (normally acceptable) accuracywill be lost due to rounding. The exception is supported for applications that need toperform exact arithmetic only. Because the rounded result is generally satisfactoryfor most applications, this exception is commonly masked.If the inexact-result exception is masked when an inexact-result condition occurs anda numeric overflow or underflow condition has not occurred, the processor sets thePE flag and stores the rounded result in the destination operand.
The currentrounding mode determines the method used to round the result. See Section 4.8.4,“Rounding.”If the inexact-result exception is not masked when an inexact result occurs andnumeric overflow or underflow has not occurred, the PE flag is set, the rounded resultis stored in the destination operand, and a software exception handler is invoked.If an inexact result occurs in conjunction with numeric overflow or underflow, one ofthe following operations is carried out:•If an inexact result occurs along with masked overflow or underflow, the OE flagor UE flag and the PE flag are set and the result is stored as described for theoverflow or underflow exceptions; see Section 4.9.1.4, “Numeric OverflowException (#O),” or Section 4.9.1.5, “Numeric Underflow Exception (#U).” If theinexact result exception is unmasked, the processor also invokes a softwareexception handler.•If an inexact result occurs along with unmasked overflow or underflow and thedestination operand is a register, the OE or UE flag and the PE flag are set, theresult is stored as described for the overflow or underflow exceptions, and asoftware exception handler is invoked.If an unmasked numeric overflow or underflow exception occurs and the destinationoperand is a memory location (which can happen only for a floating-point store), theinexact-result condition is not reported and the C1 flag is cleared.See the following sections for information regarding the inexact-result exceptionwhen detected while executing x87 FPU or SSE/SSE2/SSE3 instructions:••x87 FPU; Section 8.5.6, “Inexact-Result (Precision) Exception (#P)”SIMD floating-point exceptions; Section 11.5.2.3, “Divide-By-Zero Exception(#Z)”4.9.2Floating-Point Exception PriorityThe processor handles exceptions according to a predetermined precedence.
Whenan instruction generates two or more exception conditions, the exception precedencesometimes results in the higher-priority exception being handled and the lowerpriority exceptions being ignored. For example, dividing an SNaN by zero can potentially signal an invalid-operation exception (due to the SNaN operand) and a divideby-zero exception. Here, if both exceptions are masked, the processor handles thehigher-priority exception only (the invalid-operation exception), returning a QNaN tothe destination. Alternately, a denormal-operand or inexact-result exception can4-30 Vol. 1DATA TYPESaccompany a numeric underflow or overflow exception with both exceptions beinghandled.The precedence for floating-point exceptions is as follows:1. Invalid-operation exception, subdivided as follows:a. stack underflow (occurs with x87 FPU only)b.
stack overflow (occurs with x87 FPU only)c.operand of unsupported format (occurs with x87 FPU only when using thedouble extended-precision floating-point format)d. SNaN operand2. QNaN operand. Though this is not an exception, the handling of a QNaN operandhas precedence over lower-priority exceptions. For example, a QNaN divided byzero results in a QNaN, not a zero-divide exception.3. Any other invalid-operation exception not mentioned above or a divide-by-zeroexception.4.
Denormal-operand exception. If masked, then instruction execution continuesand a lower-priority exception can occur as well.5. Numeric overflow and underflow exceptions; possibly in conjunction with theinexact-result exception.6. Inexact-result exception.Invalid operation, zero divide, and denormal operand exceptions are detected beforea floating-point operation begins. Overflow, underflow, and precision exceptions arenot detected until a true result has been computed. When an unmasked pre-operation exception is detected, the destination operand has not yet been updated, andappears as if the offending instruction has not been executed. When an unmaskedpost-operation exception is detected, the destination operand may be updated witha result, depending on the nature of the exception (except for SSE/SSE2/SSE3instructions, which do not update their destination operands in such cases).4.9.3Typical Actions of a Floating-Point Exception HandlerAfter the floating-point exception handler is invoked, the processor handles theexception in the same manner that it handles non-floating-point exceptions.
Thefloating-point exception handler is normally part of the operating system or executive software, and it usually invokes a user-registered floating-point exceptionhandle.A typical action of the exception handler is to store state information in memory.Other typical exception handler actions include:••Examining the stored state information to determine the nature of the errorTaking actions to correct the condition that caused the errorVol.
1 4-31DATA TYPES••Clearing the exception flagsReturning to the interrupted program and resuming normal executionIn lieu of writing recovery procedures, the exception handler can do the following:•••Increment in software an exception counter for later display or printingPrint or display diagnostic information (such as the state information)Halt further program execution4-32 Vol. 1CHAPTER 5INSTRUCTION SET SUMMARYThis chapter provides an abridged overview of Intel 64 and IA-32 instructions.Instructions are divided into the following groups:•••••••••••General purposex87 FPUx87 FPU and SIMD state managementIntel MMX technologySSE extensionsSSE2 extensionsSSE3 extensionsSSSE3 extensionsSystem instructionsIA-32e mode: 64-bit mode instructionsVMX instructionsTable 5-1 lists the groups and IA-32 processors that support each group.
Withinthese groups, most instructions are collected into functional subgroups.Table 5-1. Instruction Groups and IA-32 ProcessorsInstruction SetArchitectureIntel 64 and IA-32 Processor SupportGeneral PurposeAll Intel 64 and IA-32 processorsx87 FPUIntel486, Pentium, Pentium with MMX Technology, Celeron, PentiumPro, Pentium II, Pentium II Xeon, Pentium III, Pentium III Xeon,Pentium 4, Intel Xeon processors, Pentium M, Intel Core Solo, Intel CoreDuo, Intel Core 2 Duo processorsx87 FPU and SIMD StateManagementPentium II, Pentium II Xeon, Pentium III, Pentium III Xeon, Pentium 4,Intel Xeon processors, Pentium M, Intel Core Solo, Intel Core Duo, IntelCore 2 Duo processorsMMX TechnologyPentium with MMX Technology, Celeron, Pentium II, Pentium II Xeon,Pentium III, Pentium III Xeon, Pentium 4, Intel Xeon processors,Pentium M, Intel Core Solo, Intel Core Duo, Intel Core 2 Duo processorsSSE ExtensionsPentium III, Pentium III Xeon, Pentium 4, Intel Xeon processors,Pentium M, Intel Core Solo, Intel Core Duo, Intel Core 2 Duo processorsSSE2 ExtensionsPentium 4, Intel Xeon processors, Pentium M, Intel Core Solo, Intel CoreDuo, Intel Core 2 Duo processorsVol.
1 5-1INSTRUCTION SET SUMMARYTable 5-1. Instruction Groups and IA-32 Processors (Contd.)Instruction SetArchitectureIntel 64 and IA-32 Processor SupportSSE3 ExtensionsPentium 4 supporting HT Technology (built on 90nm processtechnology), Intel Core Solo, Intel Core Duo, Intel Core 2 Duo processorsSSSE3 ExtensionsIntel Xeon processor 5100 series, Intel Core Solo, Intel Core Duo, IntelCore 2 Duo processorsIA-32e mode: 64-bitmode instructionsAll Intel 64 processorsSystem InstructionsAll Intel 64 and IA-32 processorsVMX InstructionsAll Intel 64 and IA-32 processors supporting Intel VirtualizationTechnologyThe following sections list instructions in each major group and subgroup.
Given foreach instruction is its mnemonic and descriptive names. When two or moremnemonics are given (for example, CMOVA/CMOVNBE), they represent differentmnemonics for the same instruction opcode. Assemblers support redundantmnemonics for some instructions to make it easier to read code listings. For instance,CMOVA (Conditional move if above) and CMOVNBE (Conditional move if not below orequal) represent the same condition. For detailed information about specific instructions, see the Intel® 64 and IA-32 Architectures Software Developer’s Manual,Volumes 3A & 3B.5.1GENERAL-PURPOSE INSTRUCTIONSThe general-purpose instructions preform basic data movement, arithmetic, logic,program flow, and string operations that programmers commonly use to write application and system software to run on Intel 64 and IA-32 processors.
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