Volume 1 Application Programming (794095), страница 12
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Program addresses accesslocations that can be anywhere in the linear 64-bit address space. The operating system can useseparate selectors for code, stack, and data segments for memory-protection purposes, but the baseaddress of all these segments is always 0. (For an exception to this general rule, see “FS and GS asBase of Address Calculation” on page 17.)Compatibility mode—This mode uses a protected, multi-segment model of virtual memory, just asin legacy protected mode. The 32-bit virtual-memory space is treated as a segmented set of addressspaces for code, stack, and data segments, each with its own base address and protectionparameters.
A segmented space is specified by adding a segment selector to an address.Memory Model9AMD64 Technology24592—Rev. 3.13—July 200764-Bit Mode(Flat Segmentation Model)264 - 1Legacy and Compatibility Mode(Multi-Segment Model)232 - 1Code Segment (CS) BaseStack Segment (SS) BaseBase Address forAll Segments0Data Segment (DS) Basecodestackdata0513-107.epsFigure 2-1. Virtual-Memory SegmentationOperating systems have used segmented memory as a method to isolate programs from the data theyused, in an effort to increase the reliability of systems running multiple programs simultaneously.However, most modern operating systems do not use the segmentation features available in the legacyx86 architecture.
Instead, these operating systems handle segmentation functions entirely in software.For this reason, the AMD64 architecture dispenses with most of the legacy segmentation functions in64-bit mode. This allows 64-bit operating systems to be coded more simply, and it supports moreefficient management of multi-tasking environments than is possible in the legacy x86 architecture.2.1.2 Segment RegistersSegment registers hold the selectors used to access memory segments. Figure 2-2 on page 11 showsthe application-visible portion of the segment registers. In legacy and compatibility modes, all segmentregisters are accessible to software. In 64-bit mode, only the CS, FS, and GS segments are recognizedby the processor, and software can use the FS and GS segment-base registers as base registers foraddress calculation, as described in “FS and GS as Base of Address Calculation” on page 17.
Forreferences to the DS, ES, or SS segments in 64-bit mode, the processor assumes that the base for eachof these segments is zero, neither their segment limit nor attributes are checked, and the processorsimply checks that all such addresses are in canonical form, as described in “64-Bit CanonicalAddresses” on page 15.10Memory Model24592—Rev. 3.13—July 2007AMD64 TechnologyLegacy Mode andCompatibility ModeCSCS1564-BitMode(Attributes only)DSignoredESignoredFS(Base only)GS(Base only)SSignoredFSGS0150513-312.epsFigure 2-2.Segment RegistersFor details on segmentation and the segment registers, see “Segmented Virtual Memory” in Volume 2.2.1.3 Physical MemoryPhysical memory is the installed memory (excluding cache memory) in a particular computer systemthat can be accessed through the processor’s bus interface.
The maximum size of the physical memoryspace is determined by the number of address bits on the bus interface. In a virtual-memory system, thelarge virtual-address space (also called linear-address space) is translated to a smaller physicaladdress space by a combination of segmentation and paging hardware and software.Segmentation is illustrated in Figure 2-1 on page 10. Paging is a mechanism for translating linear(virtual) addresses into fixed-size blocks called pages, which the operating system can move, asneeded, between memory and external storage media (typically disk).
The AMD64 architecturesupports an expanded version of the legacy x86 paging mechanism, one that is able to translate the full64-bit virtual-address space into the physical-address space supported by the particularimplementation.2.1.4 Memory ManagementMemory management strategies translate addresses generated by programs into addresses in physicalmemory using segmentation and/or paging. Memory management is not visible to applicationprograms. It is handled by the operating system and processor hardware. The following descriptiongives a very brief overview of these functions. Details are given in “System-Management Instructions”in Volume 2.Memory Model11AMD64 Technology24592—Rev. 3.13—July 2007Long-Mode Memory Management.
Figure 2-3 shows the flow, from top to bottom, of memorymanagement functions performed in the two submodes of long mode.64-Bit ModeCompatibility Mode63015Virtual (Linear) Address0Selector310Effective AddressSegmentation6332 31Virtual Address0PagingPaging510051Physical Address0Physical Address513-184.epsFigure 2-3. Long-Mode Memory ManagementIn 64-bit mode, programs generate virtual (linear) addresses that can be up to 64 bits in size.
Thevirtual addresses are passed to the long-mode paging function, which generates physical addresses thatcan be up to 52 bits in size. (Specific implementations of the architecture can support smaller virtualaddress and physical-address sizes.)In compatibility mode, legacy 16-bit and 32-bit applications run using legacy x86 protected-modesegmentation semantics. The 16-bit or 32-bit effective addresses generated by programs are combinedwith their segments to produce 32-bit virtual (linear) addresses that are zero-extended to a maximumof 64 bits.
The paging that follows is the same long-mode paging function used in 64-bit mode. Ittranslates the virtual addresses into physical addresses. The combination of segment selector andeffective address is also called a logical address or far pointer. The virtual address is also called thelinear address.Legacy-Mode Memory Management. Figure 2-4 on page 13 shows the memory-managementfunctions performed in the three submodes of legacy mode.12Memory Model24592—Rev. 3.13—July 2007AMD64 TechnologyProtected Mode150SelectorVirtual-8086 Mode310Effective Address (EA)0 1515310EASelectorSegmentation19Linear AddressPagingPaging031Segmentation190Linear Address0Physical Address (PA)0EASelector0Linear AddressPhysical Address (PA)0 1515Segmentation031Real Mode311900PA513-185.epsFigure 2-4.
Legacy-Mode Memory ManagementThe memory-management functions differ, depending on the submode, as follows:•••Protected Mode—Protected mode supports 16-bit and 32-bit programs with table-based memorysegmentation, paging, and privilege-checking. The segmentation function takes 32-bit effectiveaddresses and 16-bit segment selectors and produces 32-bit linear addresses into one of 16Kmemory segments, each of which can be up to 4GB in size. Paging is optional. The 32-bit physicaladdresses are either produced by the paging function or the linear addresses are used withoutmodification as physical addresses.Virtual-8086 Mode—Virtual-8086 mode supports 16-bit programs running as tasks underprotected mode.
20-bit linear addresses are formed in the same way as in real mode, but they canoptionally be translated through the paging function to form 32-bit physical addresses that accessup to 4GB of memory space.Real Mode—Real mode supports 16-bit programs using register-based shift-and-addsegmentation, but it does not support paging. Sixteen-bit effective addresses are zero-extended andadded to a 16-bit segment-base address that is left-shifted four bits, producing a 20-bit linearaddress. The linear address is zero-extended to a 32-bit physical address that can access up to 1MBof memory space.Memory Model13AMD64 Technology2.224592—Rev. 3.13—July 2007Memory Addressing2.2.1 Byte OrderingInstructions and data are stored in memory in little-endian byte order.
Little-endian ordering places theleast-significant byte of the instruction or data item at the lowest memory address and the mostsignificant byte at the highest memory address.Figure 2-5 shows a generalization of little-endian memory and register images of a quadword datatype. The least-significant byte is at the lowest address in memory and at the right-most byte locationof the register image.Quadword in Memorybyte 707hbyte 606hbyte 505hbyte 404hbyte 303hbyte 202hbyte 101hbyte 000hHigh (most-significant)Low (least-significant)Low (least-significant)High (most-significant)Quadword in General-Purpose Registerbyte 7byte 6byte 5byte 4byte 3byte 263byte 1byte 00513-116.epsFigure 2-5.Byte OrderingFigure 2-6 on page 15 shows the memory image of a 10-byte instruction.
Instructions are byte datatypes. They are read from memory one byte at a time, starting with the least-significant byte (lowestaddress). For example, the following instruction specifies the 64-bit instruction MOV RAX,1122334455667788 instruction that consists of the following ten bytes:48 B8 887766554433221148 is a REX instruction prefix that specifies a 64-bit operand size, B8 is the opcode that—together withthe REX prefix—specifies the 64-bit RAX destination register, and 8877665544332211 is the 8-byteimmediate value to be moved, where 88 represents the eighth (least-significant) byte and 11 represents14Memory Model24592—Rev. 3.13—July 2007AMD64 Technologythe first (most-significant) byte.
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