Volume 1 Application Programming (794095), страница 14
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System-programming details on the stack segments are described in “Segmented VirtualMemory” in Volume 2.2.5Instruction PointerThe instruction pointer is used in conjunction with the code-segment (CS) register to locate the nextinstruction in memory. The instruction-pointer register contains the displacement (offset)—from thebase address of the current CS segment, or from address 0 in 64-bit mode—to the next instruction to beexecuted. The pointer is incremented sequentially, except for branch instructions, as described in“Control Transfers” on page 76.In legacy and compatibility modes, the instruction pointer is a 16-bit (IP) or 32-bit (EIP) register. In64-bit mode, the instruction pointer is extended to a 64-bit (RIP) register to support 64-bit offsets. Thecase-sensitive acronym, rIP, is used to refer to any of these three instruction-pointer sizes, dependingon the software context.Figure 2-10 on page 21 shows the relationship between RIP, EIP, and IP.
The 64-bit RIP can be usedfor RIP-relative addressing, as described in “RIP-Relative Addressing” on page 18.20Memory Model24592—Rev. 3.13—July 2007AMD64 TechnologyIPEIPrIPRIP6332 310513-140.epsFigure 2-10. Instruction Pointer (rIP) RegisterThe contents of the rIP are not directly readable by software. However, the rIP is pushed onto the stackby a call instruction.The memory model described in this chapter is used by all of the programming environments thatmake up the AMD64 architecture. The next four chapters of this volume describe the applicationprogramming environments, which include:••••General-purpose programming (Chapter 3 on page 23).128-bit media programming (Chapter 4 on page 105).64-bit media programming (Chapter 5 on page 193).x87 floating-point programming (Chapter 6 on page 237).Memory Model21AMD64 Technology2224592—Rev.
3.13—July 2007Memory Model24592—Rev. 3.13—July 20073AMD64 TechnologyGeneral-Purpose ProgrammingThe general-purpose programming model includes the general-purpose registers (GPRs), integerinstructions and operands that use the GPRs, program-flow control methods, memory optimizationmethods, and I/O. This programming model includes the original x86 integer-programmingarchitecture, plus 64-bit extensions and a few additional instructions. Only the applicationprogramming instructions and resources are described in this chapter. Integer instructions typicallyused in system programming, including all of the privileged instructions, are described in Volume 2,along with other system-programming topics.The general-purpose programming model is used to some extent by almost all programs, includingprograms consisting primarily of 128-bit media instructions, 64-bit media instructions, x87 floatingpoint instructions, or system instructions.
For this reason, an understanding of the general-purposeprogramming model is essential for any programming work using the AMD64 instruction setarchitecture.3.1RegistersFigure 3-1 on page 24 shows an overview of the registers used in general-purpose applicationprogramming. They include the general-purpose registers (GPRs), segment registers, flags register,and instruction-pointer register. The number and width of available registers depends on the operatingmode.The registers and register ranges shaded light gray in Figure 3-1 on page 24 are available only in 64-bitmode. Those shaded dark gray are available only in legacy mode and compatibility mode.
Thus, in 64bit mode, the 32-bit general-purpose, flags, and instruction-pointer registers available in legacy modeand compatibility mode are extended to 64-bit widths, eight new GPRs are available, and the DS, ES,and SS segment registers are ignored.When naming registers, if reference is made to multiple register widths, a lower-case r notation isused.
For example, the notation rAX refers to the 16-bit AX, 32-bit EAX, or 64-bit RAX register,depending on an instruction’s effective operand size.General-Purpose Programming23AMD64 Technology24592—Rev. 3.13—July 2007General-Purpose Registers (GPRs)rAXrBXrCXrDXrBPrSIrDIrSPR8R9R10R11R12SegmentRegistersR13CSR14DSR1563ES0Flags and Instruction Pointer RegistersFS1532 31GSrFLAGSSSrIP06332 310Available to sofware in all modesAvailable to sofware only in 64-bit modeIgnored by hardware in 64-bit modeFigure 3-1.513-131.epsGeneral-Purpose Programming Registers3.1.1 Legacy RegistersIn legacy and compatibility modes, all of the legacy x86 registers are available. Figure 3-2 on page 25shows a detailed view of the GPR, flag, and instruction-pointer registers.24General-Purpose Programming24592—Rev.
3.13—July 2007AMD64 Technologyregisterencodinghigh8-bitlow8-bit16-bit32-bit0AH (4)ALAXEAX3BH (7)BLBXEBX1CH (5)CLCXECX2DH (6)DLDXEDX6SISIESI7DIDIEDI5BPBPEBP4SPSPESP3116 150FLAGSFLAGS EFLAGSIP31IPEIP0513-311.epsFigure 3-2.General Registers in Legacy and Compatibility ModesThe legacy GPRs include:•••Eight 8-bit registers (AH, AL, BH, BL, CH, CL, DH, DL).Eight 16-bit registers (AX, BX, CX, DX, DI, SI, BP, SP).Eight 32-bit registers (EAX, EBX, ECX, EDX, EDI, ESI, EBP, ESP).The size of register used by an instruction depends on the effective operand size or, for certaininstructions, the opcode, address size, or stack size.
The 16-bit and 32-bit registers are encoded as 0through 7 in Figure 3-2. For opcodes that specify a byte operand, registers encoded as 0 through 3 referto the low-byte registers (AL, BL, CL, DL) and registers encoded as 4 through 7 refer to the high-byteregisters (AH, BH, CH, DH).The 16-bit FLAGS register, which is also the low 16 bits of the 32-bit EFLAGS register, shown inFigure 3-2, contains control and status bits accessible to application software, as described inSection 3.1.4, “Flags Register,” on page 33. The 16-bit IP or 32-bit EIP instruction-pointer registercontains the address of the next instruction to be executed, as described in Section 2.5, “InstructionPointer,” on page 20.General-Purpose Programming25AMD64 Technology24592—Rev.
3.13—July 20073.1.2 64-Bit-Mode RegistersIn 64-bit mode, eight new GPRs are added to the eight legacy GPRs, all 16 GPRs are 64 bits wide, andthe low bytes of all registers are accessible. Figure 3-3 on page 27 shows the GPRs, flags register, andinstruction-pointer register available in 64-bit mode. The GPRs include:•••••Sixteen 8-bit low-byte registers (AL, BL, CL, DL, SIL, DIL, BPL, SPL, R8B, R9B, R10B, R11B,R12B, R13B, R14B, R15B).Four 8-bit high-byte registers (AH, BH, CH, DH), addressable only when no REX prefix is used.Sixteen 16-bit registers (AX, BX, CX, DX, DI, SI, BP, SP, R8W, R9W, R10W, R11W, R12W,R13W, R14W, R15W).Sixteen 32-bit registers (EAX, EBX, ECX, EDX, EDI, ESI, EBP, ESP, R8D, R9D, R10D, R11D,R12D, R13D, R14D, R15D).Sixteen 64-bit registers (RAX, RBX, RCX, RDX, RDI, RSI, RBP, RSP, R8, R9, R10, R11, R12,R13, R14, R15).The size of register used by an instruction depends on the effective operand size or, for certaininstructions, the opcode, address size, or stack size.
For most instructions, access to the extended GPRsrequires a REX prefix (Section 3.5.2, “REX Prefixes,” on page 74). The four high-byte registers (AH,BH, CH, DH) available in legacy mode are not addressable when a REX prefix is used.In general, byte and word operands are stored in the low 8 or 16 bits of GPRs without modifying theirhigh 56 or 48 bits, respectively. Doubleword operands, however, are normally stored in the low 32 bitsof GPRs and zero-extended to 64 bits.The 64-bit RFLAGS register, shown in Figure 3-3 on page 27, contains the legacy EFLAGS in its low32-bit range. The high 32 bits are reserved.
They can be written with anything but they always read aszero (RAZ). The 64-bit RIP instruction-pointer register contains the address of the next instruction tobe executed, as described in Section 3.1.5, “Instruction Pointer Register,” on page 36.26General-Purpose Programming24592—Rev. 3.13—July 2007AMD64 Technologynot modified for 8-bit operandsnot modified for 16-bit operandszero-extendedfor 32-bit operandsregisterencodinglow8-bit16-bit32-bit64-bit0AH*ALAXEAXRAX3BH*BLBXEBXRBX1CH*CLCXECXRCX2DH*DLDXEDXRDX6SIL**SIESIRSI7DIL**DIEDIRDI5BPL**BPEBPRBP4SPL**SPESPRSP8R8BR8WR8DR89R9BR9WR9DR910R10BR10WR10DR1011R11BR11WR11DR1112R12BR12WR12DR1213R13BR13WR13DR1314R14BR14WR14DR1415R15BR15WR15DR156332 3116 158 700RFLAGS513-309.epsRIP6332 310* Not addressable whena REX prefix is used.** Only addressable whena REX prefix is used.Figure 3-3.General Registers in 64-Bit ModeFigure 3-4 on page 28 illustrates another way of viewing the 64-bit-mode GPRs, showing how thelegacy GPRs overlap the extended GPRs.
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