Volume 1 Application Programming (794095), страница 17
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If a single BCD digit is stored per byte, it is referred to as unpacked-BCD.In the x87 floating-point programming environment (described in Section 6, “x87 Floating-PointProgramming,” on page 237) an 80-bit packed BCD data type is also supported, along withconversions between floating-point and BCD data types, so that data expressed in the BCD format canbe operated on as floating-point values.Integer add, subtract, multiply, and divide instructions can be used to operate on single (unpacked)BCD digits.
The result must be adjusted to produce a correct BCD representation. For unpacked BCDnumbers, the ASCII-adjust instructions are provided to simplify that correction. In the case of division,the adjustment must be made prior to executing the integer-divide instruction.Similarly, integer add and subtract instructions can be used to operate on packed-BCD digits.
Theresult must be adjusted to produce a correct packed-BCD representation. Decimal-adjust instructionsare provided to simplify packed-BCD result corrections.Strings. Strings are a continuous sequence of a single data type. The string instructions can be used tooperate on byte, word, doubleword, or quadword data types. The maximum length of a string of anydata type is 232–1 bytes, in legacy or compatibility modes, or 264–1 bytes in 64-bit mode.
One of themore common types of strings used by applications are byte data-type strings known as ASCII strings,which can be used to represent character data.Bit strings are also supported by instructions that operate specifically on bit strings. In general, bitstrings can start and end at any bit location within any byte, although the BTx bit-string instructionsassume that strings start on a byte boundary. The length of a bit string can range in size from a singlebit up to 232–1 bits, in legacy or compatibility modes, or 264-–1 bits in 64-bit mode.38General-Purpose Programming24592—Rev.
3.13—July 2007AMD64 Technology3.2.2 Operand Sizes and OverridesDefault Operand Size. In legacy and compatibility modes, the default operand size is either 16 bitsor 32 bits, as determined by the default-size (D) bit in the current code-segment descriptor (for details,see “Segmented Virtual Memory” in Volume 2). In 64-bit mode, the default operand size for mostinstructions is 32 bits.Application software can override the default operand size by using an operand-size instruction prefix.Table 3-3 shows the instruction prefixes for operand-size overrides in all operating modes. In 64-bitmode, the default operand size for most instructions is 32 bits.
A REX prefix (see Section 3.5.2, “REXPrefixes,” on page 74) specifies a 64-bit operand size, and a 66h prefix specifies a 16-bit operand size.The REX prefix takes precedence over the 66h prefix.Table 3-3.Operand-Size OverridesOperating Mode64-BitModeLongModeDefaultOperandSize (Bits)23232CompatibilityMode16Legacy Mode(Protected, Virtual-8086,or Real Mode)3216EffectiveOperandSize(Bits)Instruction Prefix66h1REX64xyes32nono16yesno32no16yes32yes16no32no16yes32yes16noNotApplicableNote:1.
A “no” indicates that the default operand size is used. An “x” means “don’t care.”2. Near branches, instructions that implicitly reference the stack pointer, and certainother instructions default to 64-bit operand size. See “General-Purpose Instructionsin 64-Bit Mode” in Volume 3There are several exceptions to the 32-bit operand-size default in 64-bit mode, including near branchesand instructions that implicitly reference the RSP stack pointer. For example, the near CALL, nearJMP, Jcc, LOOPcc, POP, and PUSH instructions all default to a 64-bit operand size in 64-bit mode.Such instructions do not need a REX prefix for the 64-bit operand size. For details, see “GeneralPurpose Instructions in 64-Bit Mode” in Volume 3.Effective Operand Size.
The term effective operand size describes the operand size for the currentinstruction, after accounting for the instruction’s default operand size and any operand-size override orREX prefix that is used with the instruction.General-Purpose Programming39AMD64 Technology24592—Rev.
3.13—July 2007Immediate Operand Size. In legacy mode and compatibility modes, the size of immediate operandscan be 8, 16, or 32 bits, depending on the instruction. In 64-bit mode, the maximum size of animmediate operand is also 32 bits, except that 64-bit immediates can be copied into a 64-bit GPR usingthe MOV instruction.When the operand size of a MOV instruction is 64 bits, the processor sign-extends immediates to 64bits before using them. Support for true 64-bit immediates is accomplished by expanding thesemantics of the MOV reg, imm16/32 instructions.
In legacy and compatibility modes, theseinstructions—opcodes B8h through BFh—copy a 16-bit or 32-bit immediate (depending on theeffective operand size) into a GPR. In 64-bit mode, if the operand size is 64 bits (requires a REXprefix), these instructions can be used to copy a true 64-bit immediate into a GPR.3.2.3 Operand AddressingOperands for general-purpose instructions are referenced by the instruction's syntax or they areincorporated in the instruction as an immediate value.
Referenced operands can be in registers,memory, or I/O ports.Register Operands. Most general-purpose instructions that take register operands reference thegeneral-purpose registers (GPRs). A few general-purpose instructions reference operands in theRFLAGS register, XMM registers, or MMX™ registers.The type of register addressed is specified in the instruction syntax. When addressing GPRs or XMMregisters, the REX instruction prefix can be used to access the extended GPRs or XMM registers, asdescribed in Section 3.5, “Instruction Prefixes,” on page 71.Memory Operands.
Many general-purpose instructions can access operands in memory. Section 2.2,“Memory Addressing,” on page 14 describes the general methods and conditions for addressingmemory operands.I/O Ports. Operands in I/O ports are referenced according to the conventions described in Section 3.8,“Input/Output,” on page 90.Immediate Operands. In certain instructions, a source operand—called an immediate operand, orsimply immediate—is included as part of the instruction rather than being accessed from a register ormemory location. For details on the size of immediate operands, see “Immediate Operand Size” onpage 40.3.2.4 Data AlignmentA data access is aligned if its address is a multiple of its operand size, in bytes.
The following examplesillustrate this definition:••••40Byte accesses are always aligned. Bytes are the smallest addressable parts of memory.Word (two-byte) accesses are aligned if their address is a multiple of 2.Doubleword (four-byte) accesses are aligned if their address is a multiple of 4.Quadword (eight-byte) accesses are aligned if their address is a multiple of 8.General-Purpose Programming24592—Rev.
3.13—July 2007AMD64 TechnologyThe AMD64 architecture does not impose data-alignment requirements for accessing data in memory.However, depending on the location of the misaligned operand with respect to the width of the data busand other aspects of the hardware implementation (such as store-to-load forwarding mechanisms), amisaligned memory access can require more bus cycles than an aligned access. For maximumperformance, avoid misaligned memory accesses.Performance on many hardware implementations will benefit from observing the following operandalignment and operand-size conventions:•••Avoid misaligned data accesses.Maintain consistent use of operand size across all loads and stores. Larger operand sizes(doubleword and quadword) tend to make more efficient use of the data bus and any dataforwarding features that are implemented by the hardware.When using word or byte stores, avoid loading data from the same doubleword of memory, otherthan the identical start addresses of the stores.3.3Instruction SummaryThis section summarizes the functions of the general-purpose instructions.
The instructions areorganized by functional group—such as, data-transfer instructions, arithmetic instructions, and so on.Details on individual instructions are given in the alphabetically organized “General-PurposeInstruction Reference” in Volume 3.3.3.1 SyntaxEach instruction has a mnemonic syntax used by assemblers to specify the operation and the operandsto be used for source and destination (result) data. Figure 3-7 shows an example of the mnemonicsyntax for a compare (CMP) instruction. In this example, the CMP mnemonic is followed by twooperands, a 32-bit register or memory operand and an 8-bit immediate operand.CMP reg/mem32, imm8MnemonicFirst Source Operandand Destination OperandSecond Source OperandFigure 3-7.General-Purpose Programming513-139.epsMnemonic Syntax Example41AMD64 Technology24592—Rev.
3.13—July 2007In most instructions that take two operands, the first (left-most) operand is both a source operand andthe destination operand. The second (right-most) operand serves only as a source. Instructions canhave one or more prefixes that modify default instruction functions or operand properties. Theseprefixes are summarized in Section 3.5, “Instruction Prefixes,” on page 71. Instructions that access64-bit operands in a general-purpose register (GPR) or any of the extended GPR or XMM registersrequire a REX instruction prefix.Unless otherwise stated in this section, the word register means a general-purpose register (GPR).Several instructions affect the flag bits in the RFLAGS register. “Instruction Effects on RFLAGS” inVolume 3 summarizes the effects that instructions have on rFLAGS bits.3.3.2 Data TransferThe data-transfer instructions copy data between registers and memory.Move• MOV—Move• MOVSX—Move with Sign-Extend• MOVZX—Move with Zero-Extend• MOVD—Move Doubleword or Quadword• MOVNTI—Move Non-Temporal Doubleword or QuadwordMOVx copies a byte, word, doubleword, or quadword from a register or memory location to a registeror memory location.
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