Volume 1 Application Programming (794095), страница 20
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The value of the operand is replacedwith the result of subtracting the operand from zero.Multiply and Divide• MUL—Multiply Unsigned•••50IMUL—Signed MultiplyDIV—Unsigned DivideIDIV—Signed DivideGeneral-Purpose Programming24592—Rev. 3.13—July 2007AMD64 TechnologyThe MUL instruction performs multiplication of unsigned integer operands. The size of operands canbe byte, word, doubleword, or quadword. The product is stored in a destination which is double thesize of the source operands (multiplicand and factor).The MUL instruction's mnemonic has only one operand, which is a factor.
The multiplicand operand isalways assumed to be an accumulator register. For byte-sized multiplies, AL contains the multiplicand,and the result is stored in AX. For word-sized, doubleword-sized, and quadword-sized multiplies, rAXcontains the multiplicand, and the result is stored in rDX and rAX.The IMUL instruction performs multiplication of signed integer operands. There are forms of theIMUL instruction with one, two, and three operands, and it is thus more powerful than the MULinstruction.
The one-operand form of the IMUL instruction behaves similarly to the MUL instruction,except that the operands and product are signed integer values. In the two-operand form of IMUL, themultiplicand and product use the same register (the first operand), and the factor is specified in thesecond operand. In the three-operand form of IMUL, the product is stored in the first operand, themultiplicand is specified in the second operand, and the factor is specified in the third operand.The DIV instruction performs division of unsigned integers. The instruction divides a double-sizeddividend in AH:AL or rDX:rAX by the divisor specified in the operand of the instruction.
It stores thequotient in AL or rAX and the remainder in AH or rDX.The IDIV instruction performs division of signed integers. It behaves similarly to DIV, with theexception that the operands are treated as signed integer values.Division is the slowest of all integer arithmetic operations and should be avoided wherever possible.One possibility for improving performance is to replace division with multiplication, such as byreplacing i/j/k with i/(j*k). This replacement is possible if no overflow occurs during the computationof the product.
This can be determined by considering the possible ranges of the divisors.Increment and Decrement• DEC—Decrement by 1• INC—Increment by 1The INC and DEC instructions are used to increment and decrement, respectively, an integer operandby one. For both instructions, an operand can be a byte, word, doubleword, or quadword register ormemory location.These instructions behave in all respects like the corresponding ADD and SUB instructions, with thesecond operand as an immediate value equal to 1. The only exception is that the carry flag (CF) is notaffected by the INC and DEC instructions.Apart from their obvious arithmetic uses, the INC and DEC instructions are often used to modifyaddresses of operands.
In this case it can be desirable to preserve the value of the carry flag (to use itlater), so these instructions do not modify the carry flag.General-Purpose Programming51AMD64 Technology24592—Rev. 3.13—July 20073.3.7 Rotate and ShiftThe rotate and shift instructions perform cyclic rotation or non-cyclic shift, by a given number of bits(called the count), in a given byte-sized, word-sized, doubleword-sized or quadword-sized operand.When the count is greater than 1, the result of the rotate and shift instructions can be considered as aniteration of the same 1-bit operation by count number of times.
Because of this, the descriptions belowdescribe the result of 1-bit operations.The count can be 1, the value of the CL register, or an immediate 8-bit value. To avoid redundancy andmake rotation and shifting quicker, the count is masked to the 5 or 6 least-significant bits, dependingon the effective operand size, so that its value does not exceed 31 or 63 before the rotation or shift takesplace.Rotate••••RCL—Rotate Through Carry LeftRCR—Rotate Through Carry RightROL—Rotate LeftROR—Rotate RightThe RCx instructions rotate the bits of the first operand to the left or right by the number of bitsspecified by the source (count) operand.
The bits rotated out of the destination operand are rotated intothe carry flag (CF) and the carry flag is rotated into the opposite end of the first operand.The ROx instructions rotate the bits of the first operand to the left or right by the number of bitsspecified by the source operand. Bits rotated out are rotated back in at the opposite end. The value ofthe CF flag is determined by the value of the last bit rotated out.
In single-bit left-rotates, the overflowflag (OF) is set to the XOR of the CF flag after rotation and the most-significant bit of the result. Insingle-bit right-rotates, the OF flag is set to the XOR of the two most-significant bits. Thus, in bothcases, the OF flag is set to 1 if the single-bit rotation changed the value of the most-significant bit (signbit) of the operand. The value of the OF flag is undefined for multi-bit rotates.Bit-rotation instructions provide many ways to reorder bits in an operand.
This can be useful, forexample, in character conversion, including cryptography techniques.Shift• SAL—Shift Arithmetic Left• SAR—Shift Arithmetic Right• SHL—Shift Left• SHR—Shift Right• SHLD—Shift Left Double• SHRD—Shift Right Double52General-Purpose Programming24592—Rev. 3.13—July 2007AMD64 TechnologyThe SHx instructions (including SHxD) perform shift operations on unsigned operands. The SAxinstructions operate with signed operands.SHL and SAL instructions effectively perform multiplication of an operand by a power of 2, in whichcase they work as more-efficient alternatives to the MUL instruction.
Similarly, SHR and SARinstructions can be used to divide an operand (signed or unsigned, depending on the instruction used)by a power of 2.Although the SAR instruction divides the operand by a power of 2, the behavior is different from theIDIV instruction. For example, shifting –11 (FFFFFFF5h) by two bits to the right (i.e. divide –11 by4), gives a result of FFFFFFFDh, or –3, whereas the IDIV instruction for dividing –11 by 4 gives aresult of –2. This is because the IDIV instruction rounds off the quotient to zero, whereas the SARinstruction rounds off the remainder to zero for positive dividends, and to negative infinity for negativedividends.
This means that, for positive operands, SAR behaves like the corresponding IDIVinstruction, and for negative operands, it gives the same result if and only if all the shifted-out bits arezeroes, and otherwise the result is smaller by 1.The SAR instruction treats the most-significant bit (msb) of an operand in a special way: the msb (thesign bit) is not changed, but is copied to the next bit, preserving the sign of the result.
The leastsignificant bit (lsb) is shifted out to the CF flag. In the SAL instruction, the msb is shifted out to CFflag, and the lsb is cleared to 0.The SHx instructions perform logical shift, i.e. without special treatment of the sign bit. SHL is thesame as SAL (in fact, their opcodes are the same). SHR copies 0 into the most-significant bit, andshifts the least-significant bit to the CF flag.The SHxD instructions perform a double shift.
These instructions perform left and right shift of thedestination operand, taking the bits to copy into the most-significant bit (for the SHRD instruction) orinto the least-significant bit (for the SHLD instruction) from the source operand. These instructionsbehave like SHx, but use bits from the source operand instead of zero bits to shift into the destinationoperand. The source operand is not changed.3.3.8 Compare and TestThe compare and test instructions perform arithmetic and logical comparison of operands and setcorresponding flags, depending on the result of comparison.
These instruction are used in conjunctionwith conditional instructions such as Jcc or SETcc to organize branching and conditionally executingblocks in programs. Assembler equivalents of conditional operators in high-level languages(do…while, if…then…else, and similar) also include compare and test instructions.Compare• CMP—CompareThe CMP instruction performs subtraction of the second operand (source) from the first operand(destination), like the SUB instruction, but it does not store the resulting value in the destinationoperand. It leaves both operands intact. The only effect of the CMP instruction is to set or clear thearithmetic flags (OF, SF, ZF, AF, CF, PF) according to the result of subtraction.General-Purpose Programming53AMD64 Technology24592—Rev. 3.13—July 2007The CMP instruction is often used together with the conditional jump instructions (Jcc), conditionalSET instructions (SETcc) and other instructions such as conditional loops (LOOPcc) whose behaviordepends on flag state.Test• TEST—Test BitsThe TEST instruction is in many ways similar to the AND instruction: it performs logical conjunctionof the corresponding bits of both operands, but unlike the AND instruction it leaves the operandsunchanged.
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