Volume 1 Application Programming (794095), страница 24
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Most of them do not apply to 128-bit media, 64-bit media, or x87 floating-pointinstructions.3.4.1 Address SizeIn 64-bit mode, the following rules apply to address size:•••Defaults to 64 bits.Can be overridden to 32 bits (by means of opcode prefix 67h).Can’t be overridden to 16 bits.General-Purpose Programming67AMD64 Technology24592—Rev. 3.13—July 20073.4.2 Canonical Address FormatBits 63 through the most-significant implemented virtual-address bit must be all zeros or all ones inany memory reference.
See “64-Bit Canonical Addresses” on page 15 for details. (This rule applies tolong mode, which includes both 64-bit mode and compatibility mode.)3.4.3 Branch-Displacement SizeBranch-address displacements are 8 bits or 32 bits, as in legacy mode, but are sign-extended to 64 bitsprior to using them for address computations. See “Displacements and Immediates” on page 17 fordetails.3.4.4 Operand SizeIn 64-bit mode, the following rules apply to operand size:•••••64-Bit Operand Size Option: If an instruction’s operand size (16-bit or 32-bit) in legacy modedepends on the default-size (D) bit in the current code-segment descriptor and the operand-sizeprefix, then the operand-size choices in 64-bit mode are extended from 16-bit and 32-bit to include64 bits (with a REX prefix), or the operand size is fixed at 64 bits.
See “General-PurposeInstructions in 64-Bit Mode” in Volume 3 for details.Default Operand Size: The default operand size for most instructions is 32 bits, and a REX prefixmust be used to change the operand size to 64 bits. However, two groups of instructions default to64-bit operand size and do not need a REX prefix: (1) near branches and (2) all instructions, exceptfar branches, that implicitly reference the RSP. See “General-Purpose Instructions in 64-Bit Mode”in Volume 3 for details.Fixed Operand Size: If an instruction’s operand size is fixed in legacy mode, that operand size isusually fixed at the same size in 64-bit mode. (There are some exceptions.) For example, theCPUID instruction always operates on 32-bit operands, irrespective of attempts to override theoperand size.
See “General-Purpose Instructions in 64-Bit Mode” in Volume 3 for details.Immediate Operand Size: The maximum size of immediate operands is 32 bits, as in legacymode, except that 64-bit immediates can be MOVed into 64-bit GPRs. When the operand size is 64bits, immediates are sign-extended to 64 bits prior to using them. See “Immediate Operand Size”on page 40 for details.Shift-Count and Rotate-Count Operand Size: When the operand size is 64 bits, shifts androtates use one additional bit (6 bits total) to specify shift-count or rotate-count, allowing 64-bitshifts and rotates.3.4.5 High 32 BitsIn 64-bit mode, the following rules apply to extension of results into the high 32 bits when resultssmaller than 64 bits are written:•68Zero-Extension of 32-Bit Results: 32-bit results are zero-extended into the high 32 bits of 64-bitGPR destination registers.General-Purpose Programming24592—Rev.
3.13—July 2007••AMD64 TechnologyNo Extension of 8-Bit and 16-Bit Results: 8-bit and 16-bit results leave the high 56 or 48 bits,respectively, of 64-bit GPR destination registers unchanged.Undefined High 32 Bits After Mode Change: The processor does not preserve the upper 32 bitsof the 64-bit GPRs across changes from 64-bit mode to compatibility or legacy modes. Incompatibility and legacy mode, the upper 32 bits of the GPRs are undefined and not accessible tosoftware.3.4.6 Invalid and Reassigned InstructionsThe following general-purpose instructions are invalid in 64-bit mode:•••AAA—ASCII Adjust After AdditionAAD—ASCII Adjust Before DivisionAAM—ASCII Adjust After Multiply••••••••••••••••••AAS—ASCII Adjust After SubtractionBOUND—Check Array BoundsCALL (far absolute)—Procedure Call FarDAA—Decimal Adjust after AdditionDAS—Decimal Adjust after SubtractionINTO—Interrupt to Overflow VectorJMP (far absolute)—Jump FarLDS—Load DS Segment RegisterLES—Load ES Segment RegisterPOP DS—Pop Stack into DS SegmentPOP ES—Pop Stack into ES SegmentPOP SS—Pop Stack into SS SegmentPOPA, POPAD—Pop All to GPR Words or DoublewordsPUSH CS—Push CS Segment Selector onto StackPUSH DS—Push DS Segment Selector onto StackPUSH ES—Push ES Segment Selector onto StackPUSH SS—Push SS Segment Selector onto StackPUSHA, PUSHAD—Push All to GPR Words or DoublewordsThe following general-purpose instructions are invalid in long mode (64-bit mode and compatibilitymode):••SYSENTER—System Call (use SYSCALL instead)SYSEXIT—System Exit (use SYSRET instead)The opcodes for the following general-purpose instructions are reassigned in 64-bit mode:General-Purpose Programming69AMD64 Technology24592—Rev.
3.13—July 2007••ARPL—Adjust Requestor Privilege Level. Opcode becomes the MOVSXD instruction.DEC (one-byte opcode only)—Decrement by 1. Opcode becomes a REX prefix. Use the two-byteDEC opcode instead.•INC (one-byte opcode only)—Increment by 1. Opcode becomes a REX prefix. Use the two-byteINC opcode instead.3.4.7 Instructions with 64-Bit Default Operand SizeMost instructions default to 32-bit operand size in 64-bit mode. However, the following near branchesinstructions and instructions that implicitly reference the stack pointer (RSP) default to 64-bit operandsize in 64-bit mode:••Near Branches:- Jcc—Jump Conditional Near- JMP—Jump Near- LOOP—Loop- LOOPcc—Loop ConditionalInstructions That Implicitly Reference RSP:- ENTER—Create Procedure Stack Frame- LEAVE—Delete Procedure Stack Frame- POP reg/mem—Pop Stack (register or memory)- POP reg—Pop Stack (register)- POP FS—Pop Stack into FS Segment Register- POP GS—Pop Stack into GS Segment Register- POPF, POPFD, POPFQ—Pop to rFLAGS Word, Doubleword, or Quadword- PUSH imm32—Push onto Stack (sign-extended doubleword)- PUSH imm8—Push onto Stack (sign-extended byte)- PUSH reg/mem—Push onto Stack (register or memory)- PUSH reg—Push onto Stack (register)- PUSH FS—Push FS Segment Register onto Stack- PUSH GS—Push GS Segment Register onto Stack- PUSHF, PUSHFD, PUSHFQ—Push rFLAGS Word, Doubleword, or Quadword onto StackThe default 64-bit operand size eliminates the need for a REX prefix with these instructions whenregisters RAX–RSP (the first set of eight GPRs) are used as operands.
A REX prefix is still required ifR8–R15 (the extended set of eight GPRs) are used as operands, because the prefix is required toaddress the extended registers.The 64-bit default operand size can be overridden to 16 bits using the 66h operand-size override.However, it is not possible to override the operand size to 32 bits, because there is no 32-bit operand-70General-Purpose Programming24592—Rev. 3.13—July 2007AMD64 Technologysize override prefix for 64-bit mode. For details on the operand-size prefix, see “Instruction Prefixes”in Volume 3.For details on near branches, see “Near Branches in 64-Bit Mode” on page 85. For details oninstructions that implicitly reference RSP, see “Stack Operand-Size in 64-Bit Mode” on page 77.For details on opcodes and operand-size overrides, see “General-Purpose Instructions in 64-Bit Mode”in Volume 3.3.5Instruction PrefixesAn instruction prefix is a byte that precedes an instruction’s opcode and modifies the instruction’soperation or operands.
Instruction prefixes are of two types:••Legacy PrefixesREX PrefixesLegacy prefixes are organized into five groups, in which each prefix has a unique value. REX prefixes,which enable use of the AMD64 register extensions in 64-bit mode, are organized as a single group inwhich the value of the prefix indicates the combination of register-extension features to be enabled.3.5.1 Legacy PrefixesTable 3-7 on page 72 shows the legacy prefixes. These are organized into five groups, as shown in theleft-most column of the table. Each prefix has a unique hexadecimal value.
The legacy prefixes canappear in any order in the instruction, but only one prefix from each of the five groups can be used in asingle instruction. The result of using multiple prefixes from a single group is undefined.There are several restrictions on the use of prefixes. For example, the address-size prefix changesaddress size only for a memory operand, and only a single memory operand can be overridden in aninstruction. In general, the operand-size prefix cannot be used with x87 floating-point instructions, andwhen used with 128-bit or 64-bit media instructions that prefix acts in a special way to modify theopcode. The repeat prefixes cause repetition only with certain string instructions, and when used with128-bit or 64-bit media instructions the prefixes act in a special way to modify the opcode.
The lockprefix can be used with only a small number of general-purpose instructions.Table 3-7 on page 72 summarizes the functionality of instruction prefixes. Details about the prefixesand their restrictions are given in “Instruction Prefixes” in Volume 3.General-Purpose Programming71AMD64 TechnologyTable 3-7.24592—Rev. 3.13—July 2007Legacy Instruction PrefixesMnemonicPrefix Code(Hex)DescriptionOperand-SizeOverridenone661Changes the default operand size of a memory or registeroperand, as shown in Table 3-3 on page 39.Address-SizeOverridenone67Changes the default address size of a memory operand,as shown in Table 2-1 on page 18.CS2EForces use of the CS segment for memory operands.DS3EForces use of the DS segment for memory operands.ES26Forces use of the ES segment for memory operands.FS64Forces use of the FS segment for memory operands.GS65Forces use of the GS segment for memory operands.SS36Forces use of the SS segment for memory operands.LOCKF0Causes certain read-modify-write instructions on memoryto occur atomically.Prefix GroupSegmentOverrideLockRepeats a string operation (INS, MOVS, OUTS, LODS,and STOS) until the rCX register equals 0.REPRepeatREPE orREPZREPNE orREPNZF31F21Repeats a compare-string or scan-string operation(CMPSx and SCASx) until the rCX register equals 0 orthe zero flag (ZF) is cleared to 0.Repeats a compare-string or scan-string operation(CMPSx and SCASx) until the rCX register equals 0 orthe zero flag (ZF) is set to 1.Note:1.
When used with 128-bit or 64-bit media instructions, this prefix acts in a special-purpose way to modify the opcode.Operand-Size and Address-Size Prefixes. The operand-size and address-size prefixes allowmixing of data and address sizes on an instruction-by-instruction basis.
An instruction’s defaultaddress size can be overridden in any operating mode by using the 67h address-size prefix.Table 3-3 on page 39 shows the operand-size overrides for all operating modes. In 64-bit mode, thedefault operand size for most general-purpose instructions is 32 bits. A REX prefix (described in“REX Prefixes” on page 74) specifies a 64-bit operand size, and a 66h prefix specifies a 16-bit operandsize.
The REX prefix takes precedence over the 66h prefix.Table 2-1 on page 18 shows the address-size overrides for all operating modes. In 64-bit mode, thedefault address size is 64 bits. The address size can be overridden to 32 bits. 16-bit addresses are notsupported in 64-bit mode. In compatibility mode, the address-size prefix works the same as in thelegacy x86 architecture.For further details on these prefixes, see “Operand-Size Override Prefix” in Volume 3 and “AddressSize Override Prefix” in Volume 3.72General-Purpose Programming24592—Rev. 3.13—July 2007AMD64 TechnologySegment Override Prefix.
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