Volume 1 Application Programming (794095), страница 16
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Software loads a function code into EAX, executes the CPUID instruction, and then reads theassociated processor-feature information in EAX, EBX, ECX, and EDX.3.1.4 Flags RegisterFigure 3-5 on page 34 shows the 64-bit RFLAGS register and the flag bits visible to applicationsoftware. Bits 15–0 are the FLAGS register (accessed in legacy real and virtual-8086 modes), bits31–0 are the EFLAGS register (accessed in legacy protected mode and compatibility mode), and bits63–0 are the RFLAGS register (accessed in 64-bit mode). The name rFLAGS refers to any of the threeregister widths, depending on the current software context.General-Purpose Programming33AMD64 Technology24592—Rev.
3.13—July 20076332Reserved, RAZ3112 11 10 9O DF FSee Volume 2 for System FlagsBits111076420MnemonicOFDFSFZFAFPFCFDescriptionOverflow FlagDirection FlagSign FlagZero FlagAuxiliary Carry FlagParity FlagCarry Flag876SFZF543AF2PF10CFR/WR/WR/WR/WR/WR/WR/WR/WFigure 3-5. rFLAGS Register—Flags Visible to Application SoftwareThe low 16 bits (FLAGS portion) of rFLAGS are accessible by application software and hold thefollowing flags:••One control flag (the direction flag DF).Six status flags (carry flag CF, parity flag PF, auxiliary carry flag AF, zero flag ZF, sign flag SF,and overflow flag OF).The direction flag (DF) flag controls the direction of string operations.
The status flags provide resultinformation from logical and arithmetic operations and control information for conditional move andjump instructions.Bits 31–16 of the rFLAGS register contain flags that are accessible only to system software. Theseflags are described in “System Registers” in Volume 2. The highest 32 bits of RFLAGS are reserved.In 64-bit mode, writes to these bits are ignored. They are read as zeros (RAZ). The rFLAGS register isinitialized to 02h on reset, so that all of the programmable bits are cleared to zero.The effects that rFLAGS bit-values have on instructions are summarized in the following places:•••Conditional Moves (CMOVcc)—Table 3-4 on page 43.Conditional Jumps (Jcc)—Table 3-5 on page 55.Conditional Sets (SETcc)—Table 3-6 on page 59.The effects that instructions have on rFLAGS bit-values are summarized in “Instruction Effects onRFLAGS” in Volume 3.34General-Purpose Programming24592—Rev.
3.13—July 2007AMD64 TechnologyThe sections below describe each application-visible flag. All of these flags are readable and writable.For example, the POPF, POPFD, POPFQ, IRET, IRETD, and IRETQ instructions write all flags. Thecarry and direction flags are writable by dedicated application instructions.
Other application-visibleflags are written indirectly by specific instructions. Reserved bits and bits whose writability isprevented by the current values of system flags, current privilege level (CPL), or the current operatingmode, are unaffected by the POPFx instructions.Carry Flag (CF). Bit 0. Hardware sets the carry flag to 1 if the last integer addition or subtractionoperation resulted in a carry (for addition) or a borrow (for subtraction) out of the most-significant bitposition of the result. Otherwise, hardware clears the flag to 0.The increment and decrement instructions—unlike the addition and subtraction instructions—do notaffect the carry flag.
The bit shift and bit rotate instructions shift bits of operands into the carry flag.Logical instructions like AND, OR, XOR clear the carry flag. Bit-test instructions (BTx) set the valueof the carry flag depending on the value of the tested bit of the operand.Software can set or clear the carry flag with the STC and CLC instructions, respectively. Software cancomplement the flag with the CMC instruction.Parity Flag (PF). Bit 2. Hardware sets the parity flag to 1 if there is an even number of 1 bits in theleast-significant byte of the last result of certain operations. Otherwise (i.e., for an odd number of 1bits), hardware clears the flag to 0.
Software can read the flag to implement parity checking.Auxiliary Carry Flag (AF). Bit 4. Hardware sets the auxiliary carry flag to 1 if the last binary-codeddecimal (BCD) operation resulted in a carry (for addition) or a borrow (for subtraction) out of bit 3.Otherwise, hardware clears the flag to 0.The main application of this flag is to support decimal arithmetic operations. Most commonly, this flagis used internally by correction commands for decimal addition (AAA) and subtraction (AAS).Zero Flag (ZF).
Bit 6. Hardware sets the zero flag to 1 if the last arithmetic operation resulted in avalue of zero. Otherwise (for a non-zero result), hardware clears the flag to 0. The compare and testinstructions also affect the zero flag.The zero flag is typically used to test whether the result of an arithmetic or logical operation is zero, orto test whether two operands are equal.Sign Flag (SF).
Bit 7. Hardware sets the sign flag to 1 if the last arithmetic operation resulted in anegative value. Otherwise (for a positive-valued result), hardware clears the flag to 0. Thus, in suchoperations, the value of the sign flag is set equal to the value of the most-significant bit of the result.Depending on the size of operands, the most-significant bit is bit 7 (for bytes), bit 15 (for words), bit 31(for doublewords), or bit 63 (for quadwords).Direction Flag (DF). Bit 10. The direction flag determines the order in which strings are processed.Software can set the direction flag to 1 to specify decrementing the data pointer for the next stringinstruction (LODSx, STOSx, MOVSx, SCASx, CMPSx, OUTSx, or INSx).
Clearing the direction flagGeneral-Purpose Programming35AMD64 Technology24592—Rev. 3.13—July 2007to 0 specifies incrementing the data pointer. The pointers are stored in the rSI or rDI register. Softwarecan set or clear the flag with the STD and CLD instructions, respectively.Overflow Flag (OF). Bit 11. Hardware sets the overflow flag to 1 to indicate that the most-significant(sign) bit of the result of the last signed integer operation differed from the signs of both sourceoperands. Otherwise, hardware clears the flag to 0. A set overflow flag means that the magnitude of thepositive or negative result is too big (overflow) or too small (underflow) to fit its defined data type.The OF flag is undefined after the DIV instruction and after a shift of more than one bit. Logicalinstructions clear the overflow flag.3.1.5 Instruction Pointer RegisterThe instruction pointer register—IP, EIP, or RIP, or simply rIP for any of the three depending on thecontext—is used in conjunction with the code-segment (CS) register to locate the next instruction inmemory.
See Section 2.5, “Instruction Pointer,” on page 20 for details.3.2OperandsOperands are either referenced by an instruction's encoding or included as an immediate value in theinstruction encoding. Depending on the instruction, referenced operands can be located in registers,memory locations, or I/O ports.3.2.1 Data TypesFigure 3-6 on page 37 shows the register images of the general-purpose data types. In the generalpurpose programming environment, these data types can be interpreted by instruction syntax or thesoftware context as the following types of numbers and strings:•••••Signed (two's-complement) integers.Unsigned integers.BCD digits.Packed BCD digits.Strings, including bit strings.The double quadword data type is supported in the RDX:RAX registers by the MUL, IMUL, DIV,IDIV, and CQO instructions.
Software can interpret the data types in ways other than those shown inFigure 3-6 on page 37 but the AMD64 instruction set does not directly support such interpretationsand software must handle them entirely on its own.Table 3-2 on page 37 shows the range of representable values for the general-purpose data types.36General-Purpose Programming24592—Rev.
3.13—July 2007AMD64 TechnologySigned Integer1270DoubleQuadword16 bytes (64-bit mode only)ss8 bytes (64-bit mode only)63s4 bytes31s2 bytes15sQuadwordDoublewordWordByte70Unsigned Integer1270DoubleQuadword16 bytes (64-bit mode only)8 bytes (64-bit mode only)63Quadword4 bytes31Doubleword2 bytesWord15BytePacked BCDBCD Digit73Bit513-326.eps0Figure 3-6.General-Purpose Data TypesSigned and Unsigned Integers. The architecture supports signed and unsigned 1 byte, 2 bytes, 4byte and 8 byte integers.
The sign bit is stored in the most significant bit.Table 3-2.Representable Values of General-Purpose Data TypesData TypeSigned Integers1ByteWordDoublewordQuadwordDoubleQuadword2-27 to +(27 -1) -215 to +(215 -1) -231 to +(231 -1) -263 to +(263 -1) -2127 to +(2127 -1)Note:1. The sign bit is the most-significant bit (e.g., bit 7 for a byte, bit 15 for a word, etc.).2. The double quadword data type is supported in the RDX:RAX registers by the MUL, IMUL, DIV, IDIV, and CQOinstructions.General-Purpose Programming37AMD64 TechnologyTable 3-2.24592—Rev.
3.13—July 2007Representable Values of General-Purpose Data Types (continued)Data TypeByteWordUnsigned Integers0 to +28-1(0 to 255)0 to +216-1(0 to 65,535)Packed BCDDigitsBCD DigitDoublewordQuadwordDoubleQuadword20 to +232-10 to +264-10 to +2128-1919(0 to 4.29 x 10 ) (0 to 1.84 x 10 ) (0 to 3.40 x 1038)00 to 99multiple packed BCD-digit bytes0 to 9multiple BCD-digit bytesNote:1. The sign bit is the most-significant bit (e.g., bit 7 for a byte, bit 15 for a word, etc.).2. The double quadword data type is supported in the RDX:RAX registers by the MUL, IMUL, DIV, IDIV, and CQOinstructions.Binary-Coded-Decimal (BCD) Digits.
BCD digits have values ranging from 0 to 9. These values canbe represented in binary encoding with four bits. For example, 0000b represents the decimal number 0and 1001b represents the decimal number 9. Values ranging from 1010b to 1111b are invalid for thisdata type. Because a byte contains eight bits, two BCD digits can be stored in a single byte. This isreferred to as packed-BCD.
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