Volume 1 Application Programming (794095), страница 10
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Royer, Introduction to Protected Mode Programming, course materials for an onsiteclass, 1992.Tom Shanley, Protected Mode System Architecture, Addison Wesley, NY, 1996.SGS-Thomson Corporation, 80486DX Processor SMM Programming Manual, SGS-ThomsonCorporation, 1995.Walter A. Triebel, The 80386DX Microprocessor, Prentice-Hall, Englewood Cliffs, NJ, 1992.John Wharton, The Complete x86, MicroDesign Resources, Sebastopol, California, 1994.Web sites and newsgroups:- www.amd.com- news.comp.arch- news.comp.lang.asm.x86- news.intel.microprocessors- news.microsoftxxxPreface24592—Rev.
3.13—July 2007AMD64 Technology1Overview of the AMD64 Architecture1.1IntroductionThe AMD64 architecture is a simple yet powerful 64-bit, backward-compatible extension of theindustry-standard (legacy) x86 architecture. It adds 64-bit addressing and expands register resources tosupport higher performance for recompiled 64-bit programs, while supporting legacy 16-bit and 32-bitapplications and operating systems without modification or recompilation. It is the architectural basison which new processors can provide seamless, high-performance support for both the vast body ofexisting software and 64-bit software required for higher-performance applications.The need for a 64-bit x86 architecture is driven by applications that address large amounts of virtualand physical memory, such as high-performance servers, database management systems, and CADtools.
These applications benefit from both 64-bit addresses and an increased number of registers. Thesmall number of registers available in the legacy x86 architecture limits performance in computationintensive applications. Increasing the number of registers provides a performance boost to many suchapplications.1.1.1 AMD64 FeaturesThe AMD64 architecture introduces these features:••Register Extensions (see Figure 1-1 on page 2):- 8 additional general-purpose registers (GPRs).- All 16 GPRs are 64 bits wide.- 8 128-bit XMM registers.- Uniform byte-register addressing for all GPRs.- An instruction prefix (REX) accesses the extended registers.Long Mode (see Table 1-1 on page 2):- Up to 64 bits of virtual address.- 64-bit instruction pointer (RIP).- Instruction-pointer-relative data-addressing mode.- Flat address space.Overview of the AMD64 Architecture1AMD64 Technology24592—Rev.
3.13—July 2007General-PurposeRegisters (GPRs)64-Bit Media andFloating-Point RegistersRAXRBXRCXRDXRBPRSIRDIRSPR8R9R10R11R12R13R14R15630128-Bit MediaRegistersMMX0/FPR0MMX1/FPR1MMX2/FPR2MMX3/FPR3MMX4/FPR4MMX5/FPR5MMX6/FPR6MMX7/FPR763XMM0XMM1XMM2XMM3XMM4XMM5XMM6XMM7XMM8XMM9XMM10XMM11XMM12XMM13XMM14XMM150Flags Register0EFLAGS63RFLAGS0Instruction PointerEIP63Legacy x86 registers, supported in all modesRegister extensions, supported in 64-bit modeRIP01270Application-programming registers also include the128-bit media control-and-status register and thex87 tag-word, control-word, and status-word registers513-101.epsFigure 1-1. Application-Programming Register SetTable 1-1.Operating ModesOperating ModeLongMode64-BitModeCompatibilityModeProtectedModeLegacy Virtual-8086Mode ModeRealMode2ApplicationOperatingRecompileSystem RequiredRequiredyes64-bit OSnoLegacy 32-bit OSDefaultsTypicalAddress OperandSizeSize(bits)(bits)643232161632321616noRegisterExtensionsyesnoGPRWidth (bits)64321632no161616Legacy 16-bit OSOverview of the AMD64 Architecture24592—Rev.
3.13—July 2007AMD64 Technology1.1.2 RegistersTable 1-2 compares the register and stack resources available to application software, by operatingmode. The left set of columns shows the legacy x86 resources, which are available in the AMD64architecture’s legacy and compatibility modes. The right set of columns shows the comparableresources in 64-bit mode.
Gray shading indicates differences between the modes. These registerdifferences (not including stack-width difference) represent the register extensions shown inFigure 1-1.Table 1-2.Application Registers and Stack, by Operating Mode64-Bit Mode1Legacy and Compatibility ModesRegisteror StackNameNumberSize (bits)NameNumberSize (bits)1664EAX, EBX, ECX,EDX, EBP, ESI,EDI, ESP832RAX, RBX, RCX,RDX, RBP, RSI,RDI, RSP,R8–R15128-Bit XMMRegistersXMM0–XMM78128XMM0–XMM151612864-Bit MMXRegistersMMX0–MMX73864MMX0–MMX73864FPR0–FPR73880FPR0–FPR73880EIP132RIP164EFLAGS132RFLAGS164General-PurposeRegisters (GPRs)2x87 RegistersInstruction Pointer2Flags2Stack—16 or 32—64Note:1. Gray-shaded entries indicate differences between the modes.
These differences (except stack-width difference) arethe AMD64 architecture’s register extensions.2. This list of GPRs shows only the 32-bit registers. The 16-bit and 8-bit mappings of the 32-bit registers are alsoaccessible, as described in “Registers” on page 23.3. The MMX0–MMX7 registers are mapped onto the FPR0–FPR7 physical registers, as shown in Figure 1-1. The x87stack registers, ST(0)–ST(7), are the logical mappings of the FPR0–FPR7 physical registers.As Table 1-2 shows, the legacy x86 architecture (called legacy mode in the AMD64 architecture)supports eight GPRs.
In reality, however, the general use of at least four registers (EBP, ESI, EDI, andESP) is compromised because they serve special purposes when executing many instructions. TheAMD64 architecture’s addition of eight GPRs—and the increased width of these registers from 32 bitsto 64 bits—allows compilers to substantially improve software performance. Compilers have moreflexibility in using registers to hold variables. Compilers can also minimize memory traffic—and thusboost performance—by localizing work within the GPRs.1.1.3 Instruction SetThe AMD64 architecture supports the full legacy x86 instruction set, with additional instructions tosupport long mode (see Table 1-1 on page 2 for a summary of operating modes).
The applicationprogramming instructions are organized into three subsets, as follows:Overview of the AMD64 Architecture3AMD64 Technology••••24592—Rev. 3.13—July 2007General-Purpose Instructions—These are the basic x86 integer instructions used in virtually allprograms. Most of these instructions load, store, or operate on data located in the general-purposeregisters (GPRs) or memory. Some of the instructions alter sequential program flow by branchingto other program locations.128-Bit Media Instructions—These are the streaming SIMD extension (SSE, SSE2, SSE3,SSE4A) instructions that load, store, or operate on data located primarily in the 128-bit XMMregisters.
They perform integer and floating-point operations on vector (packed) and scalar datatypes. Because the vector instructions can independently and simultaneously perform a singleoperation on multiple sets of data, they are called single-instruction, multiple-data (SIMD)instructions.
They are useful for high-performance media and scientific applications that operateon blocks of data.64-Bit Media Instructions—These are the multimedia extension (MMX™ technology) and AMD3DNow!™ technology instructions. These instructions load, store, or operate on data locatedprimarily in the 64-bit MMX registers. Like their 128-bit counterparts, described above, theyperform integer and floating-point operations on vector (packed) and scalar data types.
Thus, theyare also SIMD instructions and are useful in media applications that operate on blocks of data.AMD no longer recommends the use of 3DNow! instructions, which have been superceded bytheir more efficient 128-bit media counterparts. Relevant recommendations are provided inChapter 5, “64-Bit Media Programming” on page 193, and in the AMD64 Programmer’s ManualVolume 4: 64-Bit Media and x87 Floating-Point Instructions.x87 Floating-Point Instructions—These are the floating-point instructions used in legacy x87applications. They load, store, or operate on data located in the x87 registers.Some of these application-programming instructions bridge two or more of the above subsets. Forexample, there are instructions that move data between the general-purpose registers and the XMM orMMX registers, and many of the integer vector (packed) instructions can operate on either XMM orMMX registers, although not simultaneously.
If instructions bridge two or more subsets, theirdescriptions are repeated in all subsets to which they apply.1.1.4 Media InstructionsMedia applications—such as image processing, music synthesis, speech recognition, full-motionvideo, and 3D graphics rendering—share certain characteristics:•••They process large amounts of data.They often perform the same sequence of operations repeatedly across the data.The data are often represented as small quantities, such as 8 bits for pixel values, 16 bits for audiosamples, and 32 bits for object coordinates in floating-point format.The 128-bit and 64-bit media instructions are designed to accelerate these applications. Theinstructions use a form of vector (or packed) parallel processing known as single-instruction, multipledata (SIMD) processing. This vector technology has the following characteristics:4Overview of the AMD64 Architecture24592—Rev.
3.13—July 2007••AMD64 TechnologyA single register can hold multiple independent pieces of data. For example, a single 128-bit XMMregister can hold 16 8-bit integer data elements, or four 32-bit single-precision floating-point dataelements.The vector instructions can operate on all data elements in a register, independently andsimultaneously. For example, a PADDB instruction operating on byte elements of two vectoroperands in 128-bit XMM registers performs 16 simultaneous additions and returns 16independent results in a single operation.128-bit and 64-bit media instructions take SIMD vector technology a step further by including specialinstructions that perform operations commonly found in media applications. For example, a graphicsapplication that adds the brightness values of two pixels must prevent the add operation from wrappingaround to a small value if the result overflows the destination register, because an overflow result canproduce unexpected effects such as a dark pixel where a bright one is expected.
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